diff options
| author | Huayang Duan <huayang.duan@mediatek.com> | 2019-04-11 19:27:39 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 09:57:42 +0000 |
| commit | b8f65ad68a0ce722012ff4fac39e2b18f0025fbe (patch) | |
| tree | afe7a6f2930e534fbc99f6e09b55b694826304f6 /src/southbridge | |
| parent | 16ad2d70caec5c0ec806b95c80128fd3213246d7 (diff) | |
mediatek/mt8183: fix mode register setting fail issue
The mode register setting of DRAM may fail without some
delay after each MR write.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly and stress test pass on Kukui.
Change-Id: I51785e90b2014994be5018bfe543245d44626242
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32284
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions