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authorAngel Pons <th3fanbus@gmail.com>2020-10-30 20:23:41 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-11-07 14:19:44 +0000
commita7174b7c1ddd227969961537f8363954e756166e (patch)
treee8bbf13a3aff2df4534c622f5fa1e57a217dc7a7 /src/southbridge
parent244a425efdd2b291ba4e347e4b79181212a5bf52 (diff)
sb/intel/lynxpoint/lpc.c: Correct GPI routing check
Code does not match comment, but this time the comment is right. Change-Id: I4e277a802c68c8a4e858b2e33e7ec69b41dd9773 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47044 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 2db4b59006..4464f919ee 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -243,7 +243,7 @@ static void pch_power_options(struct device *dev)
* Set the board's GPI routing on LynxPoint-H.
* This is done as part of GPIO configuration on LynxPoint-LP.
*/
- if (pch_is_lp())
+ if (!pch_is_lp())
pch_gpi_routing(dev, config);
/* GPE setup based on device tree configuration */