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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-12-16 17:21:13 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-12-19 17:50:03 +0000
commit94ce79d6c8d4ee04f55be0bb95feb62411ec8d88 (patch)
tree7045f0138c9e22196e951be636ce9ace22468669 /src/southbridge
parentd1371508f525542f3b75de553dc338b9100bde20 (diff)
device/pciexp: Match Max_Payload_Size between ends of a link
Ends of a PCIe link may advertise different Max_Payload_Size in their PCIe Express Capabilities, Device Capabilities block. For correct operation, both ends of the link need to have their Device Control Max_Payload_Size programmed to match and not exceed the other end's Device Capabilities. Fixes: https://ticket.coreboot.org/issues/218 Change-Id: I8b1de13e9c73abb30e5ccc792918bb4f81e5fe84 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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