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authorKyösti Mälkki <kyosti.malkki@gmail.com>2022-12-05 19:31:01 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2023-04-13 18:48:18 +0000
commit8f86fa0da17a7f5ec981fdf09ebb2c6a3c17b2f6 (patch)
tree0b77e983aacb1233bd073cefbe5b63ef1b3fe2b0 /src/southbridge
parentd76beb812915826e9dee6b7edf44d69faa5569e5 (diff)
AMD binaryPI: Declare IOAPIC IDs
There is no longer a relation between MAX_CPUS and IOAPIC IDs, start the cleanup with new declarations. Change-Id: I65888550e359e55402d99e8816ece2061cfcccbc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/pi/hudson/ioapic.h10
-rw-r--r--src/southbridge/amd/pi/hudson/sm.c3
2 files changed, 12 insertions, 1 deletions
diff --git a/src/southbridge/amd/pi/hudson/ioapic.h b/src/southbridge/amd/pi/hudson/ioapic.h
new file mode 100644
index 0000000000..757e5c83d5
--- /dev/null
+++ b/src/southbridge/amd/pi/hudson/ioapic.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_BLOCK_IOAPIC_H
+#define AMD_BLOCK_IOAPIC_H
+
+/* Since the old APIC bus isn't used any more, the IOAPIC IDs could be < CONFIG_MAX_CPUS */
+#define FCH_IOAPIC_ID (CONFIG_MAX_CPUS)
+#define GNB_IOAPIC_ID (CONFIG_MAX_CPUS + 1)
+
+#endif /* AMD_BLOCK_IOAPIC_H */
diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c
index 79d1005997..c40bf5e1c9 100644
--- a/src/southbridge/amd/pi/hudson/sm.c
+++ b/src/southbridge/amd/pi/hudson/sm.c
@@ -5,6 +5,7 @@
#include <device/pci_ids.h>
#include <device/smbus.h>
#include <arch/ioapic.h>
+#include <southbridge/amd/pi/hudson/ioapic.h>
#include "hudson.h"
#include "smbus.c"
@@ -21,7 +22,7 @@
static void sm_init(struct device *dev)
{
- setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
+ setup_ioapic(VIO_APIC_VADDR, FCH_IOAPIC_ID);
}
static int lsmbus_recv_byte(struct device *dev)