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| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2021-04-29 17:53:10 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-07 12:46:17 +0000 |
| commit | 8e23270405b4ecd27abb02af9cc8a985aa01edcf (patch) | |
| tree | ca4a76c90fe1eb09c00188d90c842e7c2da08bb6 /src/southbridge | |
| parent | 27be90424b7cb8fd51c7ff6b6812601b9d091b6b (diff) | |
mb/pcengines/apu2/OemCustomize.c: make AGESA AmdInitPost happy
Bank interleaving does not work on this platform, disable it.
Additionally enable ECC feature on SKUs supporting it. AmdIntPost
returns success thanks to these settings.
TEST=boot apu2 4GB ECC and apu3 2GB no ECC and see AGESA_SUCCESS after
AmdInitPost
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I010645f53b404341895d0545855905e81c89165e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions