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authorFelix Held <felix-coreboot@felixheld.de>2023-11-18 17:49:48 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-12-06 16:19:01 +0000
commit898757fc44e73654c8c093a754356820ea42a355 (patch)
tree1ca68cf7b274ff465523d3b9796388f49803b504 /src/southbridge
parent1bb327f2162d4ce736a632ef817e48622ae9dbc1 (diff)
sb/intel/bd82x6x: assign PCH PCI bridge ops in chipset devicetree
Since the PCI bridge in the PCH is always on the same device function, the device operations can be statically assigned in the devicetree and there's no need to bind the PCI bridge device operations to the PCI device during runtime via a list of PCI IDs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic9ca925a12e64c9a5b3bf295653bf032572ff29a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79169 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/intel/bd82x6x/pci.c14
1 files changed, 1 insertions, 13 deletions
diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c
index 382506b97a..229442121f 100644
--- a/src/southbridge/intel/bd82x6x/pci.c
+++ b/src/southbridge/intel/bd82x6x/pci.c
@@ -35,7 +35,7 @@ static void pci_init(struct device *dev)
pci_write_config16(dev, SECSTS, reg16);
}
-static struct device_operations device_ops = {
+struct device_operations bd82x6x_pci_bridge_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
@@ -43,15 +43,3 @@ static struct device_operations device_ops = {
.scan_bus = pci_scan_bridge,
.ops_pci = &pci_dev_ops_pci,
};
-
-static const unsigned short pci_device_ids[] = {
- 0x2448, /* Mobile */
- 0x244e, /* Desktop */
- 0
-};
-
-static const struct pci_driver pch_pci __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VID_INTEL,
- .devices = pci_device_ids,
-};