diff options
| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-01-06 09:14:08 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-01-06 09:14:08 +0000 |
| commit | 753169dc251e3f5e71a9f678c93b68c040aebbf0 (patch) | |
| tree | ceeb73865d95baead8572ac423ed633f2d5c5495 /src/southbridge | |
| parent | 95c50c6091cdc700c79da832f61b2a94b3e5c87c (diff) | |
Kconfig builds all boards now.
This patch also aligns the configuration of a couple of
boards more closely to what newconfig does.
Also, the romstrap inc/lds files are declared in the
Makefiles of the southbridges they belong to, instead of
some global file.
AMD CPUs have their own timer functions, so disable UDELAY_IO
for them and set HAVE_INIT_TIMER as appropriate, same for
emulation/qemu-x86.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/nvidia/mcp55/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/southbridge/via/k8t890/Makefile.inc | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc index 4b5ee8e865..c7e7e5168e 100644 --- a/src/southbridge/nvidia/mcp55/Makefile.inc +++ b/src/southbridge/nvidia/mcp55/Makefile.inc @@ -14,3 +14,6 @@ driver-y += mcp55_usb.o driver-$(CONFIG_GENERATE_ACPI_TABLES) += mcp55_fadt.o obj-y += mcp55_reset.o + +chipset_bootblock_inc += $(src)/southbridge/nvidia/mcp55/romstrap.inc +chipset_bootblock_lds += $(src)/southbridge/nvidia/mcp55/romstrap.lds diff --git a/src/southbridge/via/k8t890/Makefile.inc b/src/southbridge/via/k8t890/Makefile.inc index 0eff25e751..a04a6ce801 100644 --- a/src/southbridge/via/k8t890/Makefile.inc +++ b/src/southbridge/via/k8t890/Makefile.inc @@ -7,3 +7,6 @@ driver-y += k8t890_pcie.o driver-y += k8t890_traf_ctrl.o driver-y += k8t890_error.o driver-y += k8m890_chrome.o + +chipset_bootblock_inc += $(src)/southbridge/via/k8t890/romstrap.inc +chipset_bootblock_lds += $(src)/southbridge/via/k8t890/romstrap.lds |