diff options
| author | Martin Roth <martinroth@google.com> | 2017-01-10 16:40:45 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-01-12 18:37:55 +0100 |
| commit | 6e4cb50420b7ddfecf9388e8a3b000ecb6855054 (patch) | |
| tree | 1cdef18bf706a337db0ae66a906d362a68a299f3 /src/southbridge | |
| parent | f56c7787ba34bf9ee7799a77803c1a77b2d1be27 (diff) | |
sb/intel/fsp_rangeley: Fix NULL check in gpio.c
This should always have been an and, not an or.
The only way this would happen is if no GPIOs were getting configured,
so we shouldn't ever have a NULL here, but if we did, GPIOs would
be randomly configured, which would have 'interesting' results.
Found-by: Coverity Scan #1229633 & 1229632
Change-Id: If123372658383f84279738e1186425beba3208ca
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18095
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/gpio.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c index 2a2061cb1a..0a287c4dc4 100644 --- a/src/southbridge/intel/fsp_rangeley/gpio.c +++ b/src/southbridge/intel/fsp_rangeley/gpio.c @@ -62,7 +62,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio) /* GPIO PAD Settings */ /* CFIO Core Well Set 1 */ - if ((gpio->core.cfio_init != NULL) || (gpio->core.cfio_entrynum != 0)) { + if ((gpio->core.cfio_init != NULL) && (gpio->core.cfio_entrynum != 0)) { write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01001002); for (cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) { if (!((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0)) @@ -76,7 +76,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio) } /* CFIO SUS Well Set 1 */ - if ((gpio->sus.cfio_init != NULL) || (gpio->sus.cfio_entrynum != 0)) { + if ((gpio->sus.cfio_init != NULL) && (gpio->sus.cfio_entrynum != 0)) { write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01001002); for (cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) { if (!((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0)) |