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author | Johnny Lin <johnny_lin@wiwynn.com> | 2020-06-30 11:29:56 +0800 |
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committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2020-07-04 11:15:11 +0000 |
commit | 54a7f41de181de72f622c1e0ca7cea89829257a2 (patch) | |
tree | 1551f48c06d05adb20be1d1277374cd29315409b /src/southbridge | |
parent | 99198b2f7624f2293c849c6b7a96e10c84129555 (diff) |
soc/intel/xeon_sp: Add read CPU PPIN MSR function
These changes are in accordance with the documentation:
[*] page 208-209
Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
Volume 4: Model-Specific Registers. May 2019.
Order Number: 335592-070US
Tested on OCP Tioga Pass and Delta Lake.
Change-Id: I8c2eac055a065c06859a3cb7b48ed59f15ae2fc4
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42901
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions