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authorStefan Reinauer <stepan@coresystems.de>2009-02-15 02:53:18 +0000
committerStefan Reinauer <stepan@openbios.org>2009-02-15 02:53:18 +0000
commit5389c7f72b251a7e02df892271adac791e7d0266 (patch)
treebb092a2c6f09b98e8b90f6aba231fa5d196e4e70 /src/southbridge
parenta175533dc34cd8b2c98b47124cae2bbd7fcb10d4 (diff)
- Fix up amd pistachio and dbm690t.
- make uma_memory_base and uma_memory_size uint64_t as they may be 64bit BARs on some platforms. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/rs690/rs690_cmn.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/amd/rs690/rs690_cmn.c b/src/southbridge/amd/rs690/rs690_cmn.c
index d50a48547c..302664f3c9 100644
--- a/src/southbridge/amd/rs690/rs690_cmn.c
+++ b/src/southbridge/amd/rs690/rs690_cmn.c
@@ -307,10 +307,10 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
*/
void rs690_set_tom(device_t nb_dev)
{
- extern unsigned long uma_memory_start;
+ extern uint64_t uma_memory_base;
/* set TOM */
- pci_write_config32(nb_dev, 0x90, uma_memory_start);
- nbmc_write_index(nb_dev, 0x1e, uma_memory_start);
+ pci_write_config32(nb_dev, 0x90, uma_memory_base);
+ nbmc_write_index(nb_dev, 0x1e, uma_memory_base);
}