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authorFelix Held <felix-coreboot@felixheld.de>2020-12-09 15:47:59 +0100
committerFelix Held <felix-coreboot@felixheld.de>2020-12-10 16:00:55 +0000
commit3fe1ad1f26314e9926037e7b0025b65582a34a75 (patch)
tree5d678b001514a79e9d3eaea5668989a449b88136 /src/southbridge
parent244cf7d3a6d8db2a2ea5541815a0bd4e564c8195 (diff)
soc/amd/stoneyridge/reset: use port and bit defines from cf9_reset.h
The register name and the name of one bit are slightly different, but have the same functionality. Change-Id: Ie49975bb43868cbb2dc986e66dc5b7291e70222f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48507 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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