diff options
| author | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2008-12-23 17:20:46 +0000 |
|---|---|---|
| committer | Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> | 2008-12-23 17:20:46 +0000 |
| commit | 33f9633184ddc84151ab3685725d13448cdec232 (patch) | |
| tree | c10a199a36ba2e47da3a8465dc033ce045778a58 /src/southbridge | |
| parent | 5a3c8462dcd0335a0e7f950b9c91af636a727a7a (diff) | |
Handle RS690 quirks for 1 GHz noncoherent HyperTransport.
The RS690 chipset has a problem where it will not work with 1 GHz HT
speed unless NB_CFG_Q_F1000_800 bit 0 is set.
Tested, works on my Asus M2A-VM with an 1 GHz HT capable processor.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Bao, Zheng says:
As a matter of fact, both 600Mhz and 1Ghz have their own specific
setting.
This patch has been tested on dbm690t which HT link works on 800Mhz.
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/rs690/rs690_early_setup.c | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/src/southbridge/amd/rs690/rs690_early_setup.c b/src/southbridge/amd/rs690/rs690_early_setup.c index 08ce2515c4..d253f0d868 100644 --- a/src/southbridge/amd/rs690/rs690_early_setup.c +++ b/src/southbridge/amd/rs690/rs690_early_setup.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2008 Carl-Daniel Hailfinger * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -175,8 +176,9 @@ static void rs690_htinit() /* * About HT, it has been done in enumerate_ht_chain(). */ - device_t k8_f0; + device_t k8_f0, rs690_f0; u32 reg; + u8 reg8; u8 k8_ht_freq; k8_f0 = PCI_DEV(0, 0x18, 0); @@ -195,7 +197,22 @@ static void rs690_htinit() ************************/ reg = pci_read_config32(k8_f0, 0x88); k8_ht_freq = (reg & 0xf00) >> 8; - printk_info("rs690_ht_init k8_ht_freq=%x.\n", k8_ht_freq); + printk_spew("rs690_htinit k8_ht_freq=%x.\n", k8_ht_freq); + rs690_f0 = PCI_DEV(0, 0, 0); + reg8 = pci_read_config8(rs690_f0, 0x9c); + printk_spew("rs690_htinit NB_CFG_Q_F1000_800=%x\n", reg8); + /* For 1000 MHz HT, NB_CFG_Q_F1000_800 bit 0 MUST be set. + * For any other HT frequency, NB_CFG_Q_F1000_800 bit 0 MUST NOT be set. + */ + if (((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) && (!(reg8 & 0x1))) { + printk_info("rs690_htinit setting bit 0 in NB_CFG_Q_F1000_800 to use 1 GHz HT\n"); + reg8 |= 0x1; + pci_write_config8(rs690_f0, 0x9c, reg8); + } else if ((k8_ht_freq != 0x6) && (k8_ht_freq != 0xf) && (reg8 & 0x1)) { + printk_info("rs690_htinit clearing bit 0 in NB_CFG_Q_F1000_800 to not use 1 GHz HT\n"); + reg8 &= ~0x1; + pci_write_config8(rs690_f0, 0x9c, reg8); + } } /******************************************************* @@ -462,7 +479,6 @@ static void rs690_early_setup() break; } - rs690_htinit(); k8_optimization(); rs690_por_init(nb_dev); } |