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| author | Benjamin Doron <benjamin.doron@9elements.com> | 2024-04-08 15:02:03 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-04-11 19:11:54 +0000 |
| commit | 1dc8f0272bd222125d2d26cfa2b311f3d134f6ca (patch) | |
| tree | 47f631beefaa7f82c9a8983fbb98d63ca08026cc /src/southbridge | |
| parent | 09a0dc650d8f4c4ed319d302a78252c181b8db6c (diff) | |
soc/intel/alderlake: Support missing CLKREQ workaround on RaptorLake FSP
IoT variants of the RaptorLake FSP support the `PchPciePowerGating` and
`PchPcieClockGating` UPDs, so, remove the preprocessor check that only
enabled it for AlderLake FSPs.
Change-Id: I583a4b257b72f992fdb6390d00e187d04a749177
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81803
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions