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| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2015-08-02 21:29:20 -0500 |
|---|---|---|
| committer | Peter Stuge <peter@stuge.se> | 2015-10-16 21:25:28 +0000 |
| commit | cbda504eecc03f63313f054b83fc6b3c6988a9db (patch) | |
| tree | ecf90e0bd4e5b9d38fc682ef677fc76ef6a18382 /src/southbridge | |
| parent | cfbcba5db87e9d461d9ba5c5d3fb6a7754c73694 (diff) | |
southbridge/amd/sr5650: Remove unnecessary register configuration
Do not hardcode the CPU downstream non-posted request limit; the
value of this register is CPU family specific and is set appropriately
in the corresponding CPU driver code.
Change-Id: I432b942f114243cba23c9a8d916cf6d07bc4740b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11935
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/sr5650/early_setup.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index d91f3bdd90..ec555f81b2 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2010 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify @@ -437,7 +438,6 @@ static void sr5650_por_htiu_index_init(device_t nb_dev) set_htiu_enable_bits(nb_dev, 0x1D, 0x1<<2, 0x1<<2); set_htiu_enable_bits(nb_dev, 0x1D, 0x1<<4, 0x1<<4); - set_nbcfg_enable_bits(cpu_f0, 0x68, 3 << 21, 0 << 21); axindxc_reg(0x10, 1 << 9, 1 << 9); set_pcie_enable_bits(nb_dev, 0x10 | 5 << 16, 1 << 9, 1 << 9); set_htiu_enable_bits(nb_dev, 0x06, 0x1<<26, 0x1<<26); |