diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-12-19 19:10:45 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-03 11:33:54 +0000 |
| commit | 26e0f4cefc9423fafc7e105796df93026026c48c (patch) | |
| tree | d3129a510964707fa9a99df590f5d5ac91f9e544 /src/southbridge | |
| parent | 1749b77b234831bcf2c7df4fb5c3299f8a477b14 (diff) | |
sb,soc/intel: Convert some CONFIG(CHROMEOS) preprocessor
Change-Id: I964f4340caa20124a15e52c055d2f27ba5113687
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/me_common.c | 11 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/me_9.x.c | 8 |
2 files changed, 6 insertions, 13 deletions
diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index ae157d36c3..422c091001 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -15,6 +15,8 @@ #include "me.h" #include "pch.h" +#include <vendorcode/google/chromeos/chromeos.h> + /* Path that the BIOS should take based on ME state */ static const char *const me_bios_path_values[] = { [ME_NORMAL_BIOS_PATH] = "Normal", @@ -362,10 +364,6 @@ int intel_mei_setup(struct device *dev) return 0; } -#if CONFIG(CHROMEOS) -#include <vendorcode/google/chromeos/chromeos.h> -#endif - /* Read the Extend register hash of ME firmware */ int intel_me_extend_valid(struct device *dev) { @@ -405,10 +403,9 @@ int intel_me_extend_valid(struct device *dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ - chromeos_set_me_hash(extend, count); -#endif + if (CONFIG(CHROMEOS)) + chromeos_set_me_hash(extend, count); return 0; } diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 9910658b82..69192e6ccb 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -25,10 +25,7 @@ #include "me.h" #include "pch.h" -#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> -#include <vendorcode/google/chromeos/gnvs.h> -#endif /* Path that the BIOS should take based on ME state */ static const char *const me_bios_path_values[] __unused = { @@ -755,10 +752,9 @@ static int intel_me_extend_valid(struct device *dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG(CHROMEOS) /* Save hash in NVS for the OS to verify */ - chromeos_set_me_hash(extend, count); -#endif + if (CONFIG(CHROMEOS)) + chromeos_set_me_hash(extend, count); return 0; } |