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authorDave Frodin <dave.frodin@se-eng.com>2012-08-21 16:51:33 -0600
committerAnton Kochkov <anton.kochkov@gmail.com>2012-08-27 15:57:18 +0200
commit3780597cc31422dd54e385cdb508ab30467fdd51 (patch)
tree97ae2f33f64471b96913fe064815360057de15f4 /src/southbridge
parentcc6019879d7f7f7d4a9d9dba358349f0752af583 (diff)
SB700/SP5100: This configures the HPET clock period.
Prior to this change the setting would be zeroes and would cause a BSOD in 64 bit versions of Windows. Change-Id: I2d422ef9667457af53f9fd055799e489ed2b25db Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/1475 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Diffstat (limited to 'src/southbridge')
-rw-r--r--src/southbridge/amd/sb700/early_setup.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index c890ad90d3..648b0d9d78 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -420,6 +420,14 @@ static void sb700_devices_por_init(void)
byte |= 0x24;
pci_write_config8(dev, 0x62, byte);
+ /* Configure HPET Counter CLK period */
+ byte = pci_read_config8(dev, 0x43);
+ byte &= 0xF7; /* unhide HPET regs */
+ pci_write_config8(dev, 0x43, byte);
+ pci_write_config32(dev, 0x34, 0x0429B17E ); /* Counter CLK period */
+ byte |= 0x08; /* hide HPET regs */
+ pci_write_config8(dev, 0x43, byte);
+
/* Features Enable */
pci_write_config32(dev, 0x64, 0x829E79BF); /* bit10: Enables the HPET interrupt. */