From 3780597cc31422dd54e385cdb508ab30467fdd51 Mon Sep 17 00:00:00 2001 From: Dave Frodin Date: Tue, 21 Aug 2012 16:51:33 -0600 Subject: SB700/SP5100: This configures the HPET clock period. Prior to this change the setting would be zeroes and would cause a BSOD in 64 bit versions of Windows. Change-Id: I2d422ef9667457af53f9fd055799e489ed2b25db Signed-off-by: Dave Frodin Reviewed-on: http://review.coreboot.org/1475 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc Reviewed-by: Anton Kochkov --- src/southbridge/amd/sb700/early_setup.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/southbridge') diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index c890ad90d3..648b0d9d78 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -420,6 +420,14 @@ static void sb700_devices_por_init(void) byte |= 0x24; pci_write_config8(dev, 0x62, byte); + /* Configure HPET Counter CLK period */ + byte = pci_read_config8(dev, 0x43); + byte &= 0xF7; /* unhide HPET regs */ + pci_write_config8(dev, 0x43, byte); + pci_write_config32(dev, 0x34, 0x0429B17E ); /* Counter CLK period */ + byte |= 0x08; /* hide HPET regs */ + pci_write_config8(dev, 0x43, byte); + /* Features Enable */ pci_write_config32(dev, 0x64, 0x829E79BF); /* bit10: Enables the HPET interrupt. */ -- cgit v1.2.3