diff options
author | Ronald G. Minnich <rminnich@gmail.com> | 2003-09-26 17:41:21 +0000 |
---|---|---|
committer | Ronald G. Minnich <rminnich@gmail.com> | 2003-09-26 17:41:21 +0000 |
commit | 42acd12cbc5a5fe6054cdd19de76cbe35d2aef9e (patch) | |
tree | 7345aa3b5bf991827f99ee1d26bd533a884c590d /src/southbridge/via/vt8231/vt8231_early_serial.c | |
parent | 11dbdf5d782b94fb40c6f57488333d927d244975 (diff) |
serial supprt.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/via/vt8231/vt8231_early_serial.c')
-rw-r--r-- | src/southbridge/via/vt8231/vt8231_early_serial.c | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/src/southbridge/via/vt8231/vt8231_early_serial.c b/src/southbridge/via/vt8231/vt8231_early_serial.c new file mode 100644 index 0000000000..168ee07377 --- /dev/null +++ b/src/southbridge/via/vt8231/vt8231_early_serial.c @@ -0,0 +1,71 @@ +/* + * Enable the serial evices on the VIA + */ + + +/* The base address is 0x15c, 0x2e, depending on config bytes */ + +#define SIO_BASE 0x3f0 +#define SIO_DATA SIO_BASE+1 + +static void +vt8231_writesuper(uint8_t reg, uint8_t val) { + outb(reg, SIO_BASE); + outb(val, SIO_DATA); +} + +static void +vt8231_writesiobyte(uint16_t reg, uint8_t val) { + outb(val, reg); +} + +static void +vt8231_writesioword(uint16_t reg, uint16_t val) { + outw(val, reg); +} + + +/* regs we use: 85, and the southbridge devfn is defined by the + mainboard + */ + +static void +enable_vt8231_serial(void) { + device_t dev; + + dev = pci_locate_device(PCI_ID(0x1106,0x3065), 0); + + if (dev == PCI_DEV_INVALID) { + die("Serial controller not found\r\n"); + } + + + /* first, you have to enable the superio and superio config. + put a 3 in devfn 38 reg 85 + */ + pci_write_config8(dev, 0x85, 3); + // now go ahead and set up com1. + // set address + vt8231_writesuper(0xf4, 0xfe); + // enable serial out + vt8231_writesuper(0xf2, 7); + // That's it for the sio stuff. + // movl $SUPERIOCONFIG, %eax + // movb $9, %dl + // PCI_WRITE_CONFIG_BYTE + // set up reg to set baud rate. + vt8231_writesiobyte(0x3fb, 0x80); + // Set 115 kb + vt8231_writesioword(0x3f8, 1); + // Set 9.6 kb + // WRITESIOWORD(0x3f8, 12) + // now set no parity, one stop, 8 bits + vt8231_writesiobyte(0x3fb, 3); + // now turn on RTS, DRT + vt8231_writesiobyte(0x3fc, 3); + // Enable interrupts + vt8231_writesiobyte(0x3f9, 0xf); + // should be done. Dump a char for fun. + vt8231_writesiobyte(0x3f8, 48); + +} |