diff options
| author | Rudolf Marek <r.marek@assembler.cz> | 2008-09-19 22:58:59 +0000 |
|---|---|---|
| committer | Rudolf Marek <r.marek@assembler.cz> | 2008-09-19 22:58:59 +0000 |
| commit | 0b0771d180d5b18a3d698ccac54449112a9fca91 (patch) | |
| tree | df7be41b042262a4ac04f72b48ff61c71df5e0e7 /src/southbridge/via/k8t890/k8t890_bridge.c | |
| parent | c4128cfbec0d496873b9a2a684cf32a23b17137d (diff) | |
Attached patch fixes at least one issue ;) During the PCI BAR sizing must be the
D1F0 bridge without activated I/O and MEM resources, otherwise it will hang
whole PCI bus.
U-boot is also disabling the IO/MEM decode when sizing the BARs, dont know why
does we not.
Second small change just changes a bit which controls the PSTATECTL logic.
Third change deals with the integrated VGA, which needs to be enabled early,
so the VGA_EN is set along the bridges, and PCI K8 resource maps are set
correctly. Finally the CPU accessible framebuffer is now disabled as it is not
needed.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/via/k8t890/k8t890_bridge.c')
| -rw-r--r-- | src/southbridge/via/k8t890/k8t890_bridge.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/southbridge/via/k8t890/k8t890_bridge.c b/src/southbridge/via/k8t890/k8t890_bridge.c index be1ba721ef..44347127f6 100644 --- a/src/southbridge/via/k8t890/k8t890_bridge.c +++ b/src/southbridge/via/k8t890/k8t890_bridge.c @@ -24,8 +24,8 @@ static void bridge_enable(struct device *dev) { + u8 tmp; print_debug("B188 device dump\n"); - /* VIA recommends this, sorry no known info. */ writeback(dev, 0x40, 0x91); @@ -44,6 +44,12 @@ static void bridge_enable(struct device *dev) writeback(dev, 0x3e, 0x16); dump_south(dev); + + /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */ + tmp = pci_read_config8(dev, PCI_COMMAND); + tmp &= ~0x3; + pci_write_config8(dev, PCI_COMMAND, tmp); + } static const struct device_operations bridge_ops = { |