diff options
| author | Nick Vaccaro <nvaccaro@google.com> | 2017-12-20 17:18:01 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-08 18:24:05 +0000 |
| commit | cb06fab1fcb17cf9fd82b2d74c2eb2e319f2bba2 (patch) | |
| tree | 3fe00f80b6045f292ec090d40b7f1633560524ad /src/southbridge/via/common | |
| parent | 5d6ab45dbb641187f82b4e3ed7487488ccd4971c (diff) | |
soc/intel/common/block/gspi: set cs polarity before using
Move call to __gspi_cs_change() in gspi_ctrlr_setup() to after
initialization of cs polarity since it requires polarity to be
set to work properly. Failure to do so confuses cr50.
BUG=b:70628116
BRANCH=chromeos-2016.05
TEST='emerge-meowth coreboot' and verify on scope that chip select
polarity is correct for the first transaction.
Change-Id: I20b4f584663477d751a07889bccc865efbf9c469
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/25013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/southbridge/via/common')
0 files changed, 0 insertions, 0 deletions