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authorNathaniel Roach <nroach44@gmail.com>2017-09-09 19:59:07 +0800
committerMartin Roth <martinroth@google.com>2017-09-19 01:27:17 +0000
commitd7e0cb93ae8ead42aa20dd4dcafa137fc28653bc (patch)
tree13e0580e5f4d75ac145bda0a7152b3e9ff8d1a6c /src/southbridge/sis
parent2fd9651b239498a95c749ad3da140aa4d2cb06b8 (diff)
sb/intel/bd82x6x: Add awareness of ME's Alt Disable Mode
me_cleaner now allows setting a bit in the PCH straps - AltMeDisable tells the ME to stop execution after BUP - disabling the 30 minute watchdog - but also "breaking" the ME. The ME reports opmode = 2. This means the ME will not respond when we wait for an acknowledgement about the DRAM being ready. The current code waits 5 seconds for a response, that in this case, never comes. If the ME is reporting opmode 2, don't delay or wait for a response from the ME. Tested on my X220, this patch fixed the five seconds before the payload executed. Verified using the timestamp patch. Change-Id: Ifdda6b2dbb8ae3a650be6d5df6c60475a3fa74aa Signed-off-by: Nathaniel Roach <nroach44@gmail.com> Reviewed-on: https://review.coreboot.org/21466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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