diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-05 22:17:30 +0200 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-10-11 23:33:23 +0200 |
commit | 49a7c37de95531eb2f8037542806ec56240388be (patch) | |
tree | 10dca0b6e05329afe2e5f2b531087141d27f1fd7 /src/southbridge/nvidia/mcp55/lpc.c | |
parent | 571fb1fb4432d7e1e18ef610adbca6971e01573d (diff) |
southbridge/nvidia: Remove commented code
Change-Id: Ice4a5cae1a289852895012bb55035707b54cefb5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16899
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/nvidia/mcp55/lpc.c')
-rw-r--r-- | src/southbridge/nvidia/mcp55/lpc.c | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 824abc526e..afc6e647b8 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -91,11 +91,6 @@ static void lpc_init(device_t dev) lpc_common_init(dev, 1); -#if 0 - /* Posted memory write enable. */ - byte = pci_read_config8(dev, 0x46); - pci_write_config8(dev, 0x46, byte | (1 << 0)); -#endif /* power after power fail */ #if 1 @@ -122,13 +117,6 @@ static void lpc_init(device_t dev) (on * 12) + (on >> 1), (on & 1) * 5); } -#if 0 - /* Enable Port 92 fast reset (default is enabled). */ - byte = pci_read_config8(dev, 0xe8); - byte |= ~(1 << 3); - pci_write_config8(dev, 0xe8, byte); -#endif - /* Enable error reporting. */ /* Set up sync flood detected. */ byte = pci_read_config8(dev, 0x47); @@ -258,7 +246,6 @@ static struct device_operations lpc_ops = { .enable_resources = mcp55_lpc_enable_resources, .init = lpc_init, .scan_bus = scan_lpc_bus, -// .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, }; static const unsigned short lpc_ids[] = { @@ -295,7 +282,6 @@ static struct device_operations lpc_slave_ops = { .write_acpi_tables = acpi_write_hpet, #endif .init = lpc_slave_init, -// .enable = mcp55_enable, .ops_pci = &mcp55_pci_ops, }; |