diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-10-05 22:17:30 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-11 23:33:23 +0200 |
| commit | 49a7c37de95531eb2f8037542806ec56240388be (patch) | |
| tree | 10dca0b6e05329afe2e5f2b531087141d27f1fd7 /src/southbridge/nvidia/ck804/lpc.c | |
| parent | 571fb1fb4432d7e1e18ef610adbca6971e01573d (diff) | |
southbridge/nvidia: Remove commented code
Change-Id: Ice4a5cae1a289852895012bb55035707b54cefb5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16899
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/nvidia/ck804/lpc.c')
| -rw-r--r-- | src/southbridge/nvidia/ck804/lpc.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index d15ef8e178..2b0bdd536b 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -136,12 +136,6 @@ static void lpc_init(device_t dev) printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n", (on * 12) + (on >> 1), (on & 1) * 5); } -#if 0 - /* Enable Port 92 fast reset (default is enabled). */ - byte = pci_read_config8(dev, 0xe8); - byte |= ~(1 << 3); - pci_write_config8(dev, 0xe8, byte); -#endif /* Set up NMI on errors. */ byte = inb(0x70); /* RTC70 */ |