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authorJulius Werner <jwerner@chromium.org>2022-01-21 17:06:20 -0800
committerJulius Werner <jwerner@chromium.org>2022-02-07 23:29:09 +0000
commite9665959edeba6ae2d5364c4f7339704b6b6fd42 (patch)
treee3cd9e0e6e91c9b6bd5c6f586a9abee1d654b5dd /src/southbridge/intel
parent266041f0e62296737617cc2fcfa97f31e2b43aea (diff)
treewide: Remove "ERROR: "/"WARN: " prefixes from log messages
Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/early_me.c4
-rw-r--r--src/southbridge/intel/bd82x6x/early_me_mrc.c6
-rw-r--r--src/southbridge/intel/common/spi.c6
-rw-r--r--src/southbridge/intel/lynxpoint/early_me.c6
4 files changed, 11 insertions, 11 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c
index 34e0c99f26..561bed9664 100644
--- a/src/southbridge/intel/bd82x6x/early_me.c
+++ b/src/southbridge/intel/bd82x6x/early_me.c
@@ -56,14 +56,14 @@ int intel_early_me_init(void)
udelay(ME_DELAY);
}
if (!count) {
- printk(BIOS_ERR, "ERROR: ME is not ready!\n");
+ printk(BIOS_ERR, "ME is not ready!\n");
return -1;
}
/* Check for valid firmware */
hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
if (hfs.fpt_bad) {
- printk(BIOS_WARNING, "WARNING: ME has bad firmware\n");
+ printk(BIOS_WARNING, "ME has bad firmware\n");
return -1;
}
diff --git a/src/southbridge/intel/bd82x6x/early_me_mrc.c b/src/southbridge/intel/bd82x6x/early_me_mrc.c
index 2582abb680..88fad7c801 100644
--- a/src/southbridge/intel/bd82x6x/early_me_mrc.c
+++ b/src/southbridge/intel/bd82x6x/early_me_mrc.c
@@ -55,14 +55,14 @@ int intel_early_me_init(void)
udelay(ME_DELAY);
}
if (!count) {
- printk(BIOS_ERR, "ERROR: ME is not ready!\n");
+ printk(BIOS_ERR, "ME is not ready!\n");
return -1;
}
/* Check for valid firmware */
hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
if (hfs.fpt_bad) {
- printk(BIOS_WARNING, "WARNING: ME has bad firmware\n");
+ printk(BIOS_WARNING, "ME has bad firmware\n");
return -1;
}
@@ -114,7 +114,7 @@ int intel_early_me_init_done(u8 status)
udelay(ME_DELAY);
}
if (!count) {
- printk(BIOS_ERR, "ERROR: ME failed to respond\n");
+ printk(BIOS_ERR, "ME failed to respond\n");
return -1;
}
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 30f7657948..44d283c590 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -998,7 +998,7 @@ static int spi_flash_protect(const struct spi_flash *flash,
}
if (fpr == cntlr.fpr_max) {
- printk(BIOS_ERR, "ERROR: No SPI FPR free!\n");
+ printk(BIOS_ERR, "No SPI FPR free!\n");
return -1;
}
@@ -1017,7 +1017,7 @@ static int spi_flash_protect(const struct spi_flash *flash,
protect_mask |= (ICH9_SPI_FPR_RPE | SPI_FPR_WPE);
break;
default:
- printk(BIOS_ERR, "ERROR: Seeking invalid protection!\n");
+ printk(BIOS_ERR, "Seeking invalid protection!\n");
return -1;
}
@@ -1027,7 +1027,7 @@ static int spi_flash_protect(const struct spi_flash *flash,
/* Set the FPR register and verify it is protected */
write32(&fpr_base[fpr], reg);
if (reg != read32(&fpr_base[fpr])) {
- printk(BIOS_ERR, "ERROR: Unable to set SPI FPR %d\n", fpr);
+ printk(BIOS_ERR, "Unable to set SPI FPR %d\n", fpr);
return -1;
}
diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c
index 6c73c33ce0..947c570e16 100644
--- a/src/southbridge/intel/lynxpoint/early_me.c
+++ b/src/southbridge/intel/lynxpoint/early_me.c
@@ -45,14 +45,14 @@ int intel_early_me_init(void)
udelay(ME_DELAY);
}
if (!count) {
- printk(BIOS_ERR, "ERROR: ME is not ready!\n");
+ printk(BIOS_ERR, "ME is not ready!\n");
return -1;
}
/* Check for valid firmware */
hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
if (hfs.fpt_bad) {
- printk(BIOS_WARNING, "WARNING: ME has bad firmware\n");
+ printk(BIOS_WARNING, "ME has bad firmware\n");
return -1;
}
@@ -123,7 +123,7 @@ int intel_early_me_init_done(u8 status)
udelay(ME_DELAY);
}
if (!count) {
- printk(BIOS_ERR, "ERROR: ME failed to respond\n");
+ printk(BIOS_ERR, "ME failed to respond\n");
return -1;
}