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authorUwe Hermann <uwe@hermann-uwe.de>2010-09-25 23:47:15 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-09-25 23:47:15 +0000
commitdc3aa7abff4246bdbf5a6a397e758e4aa918a285 (patch)
treedf9e802de023a35c5999e897e34e3341a7cbf733 /src/southbridge/intel
parent86224f634a74bd38823c620beb647276c9c8d95c (diff)
Various Debug Port southbridge implementation fixes / cosmetics.
- Use PCI_COMMAND and PCI_COMMAND_MEMORY from pci_def.h instead of hardcoding their values. - SB600/SB700: Drop useless/unused SB600_DEVN_BASE and SB700_DEVN_BASE. - ICH7: Drop unused EHCI_CONFIG_FLAG and EHCI_PORTSC. - s/uint32_t/u32/. - Cosmetics, whitespace, coding style fixes and added code comments. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_usb_debug.c23
1 files changed, 12 insertions, 11 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c b/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
index 4fa3cb7aed..464dac2b92 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
@@ -17,16 +17,13 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <stdint.h>
#include <usbdebug.h>
+#include <device/pci_def.h>
-// An arbitrary address for the BAR
-#define EHCI_BAR 0xFEF00000
-// These could be read from DEBUG_BASE (0:1d.7 R 0x5A 16bit)
-#define EHCI_BAR_INDEX 0x10
-
-#define EHCI_CONFIG_FLAG 0x40
-#define EHCI_PORTSC 0x44
-#define EHCI_DEBUG_OFFSET 0xA0
+#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */
+#define EHCI_BAR_INDEX 0x10 /* Hardwired 0x10 (>= ICH4). */
+#define EHCI_DEBUG_OFFSET 0xA0 /* Hardwired 0xa0 (>= ICH5). */
/* Required for successful build, but currently empty. */
void set_debug_port(unsigned int port)
@@ -37,13 +34,17 @@ void set_debug_port(unsigned int port)
static void i82801gx_enable_usbdebug(unsigned int port)
{
u32 dbgctl;
+ device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
+
+ /* Set the EHCI BAR address. */
+ pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
- pci_write_config32(PCI_DEV(0, 0x1d, 7), EHCI_BAR_INDEX, EHCI_BAR);
- pci_write_config8(PCI_DEV(0, 0x1d, 7), 0x04, 0x2); // Memory Space Enable
+ /* Enable access to the EHCI memory space registers. */
+ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+ /* Force ownership of the Debug Port to the EHCI controller. */
printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
dbgctl = read32(EHCI_BAR + EHCI_DEBUG_OFFSET);
dbgctl |= (1 << 30);
write32(EHCI_BAR + EHCI_DEBUG_OFFSET, dbgctl);
}
-