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author | Bill XIE <persmule@hardenedlinux.org> | 2022-08-03 00:18:14 +0800 |
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committer | Martin L Roth <gaumless@gmail.com> | 2022-08-07 19:40:28 +0000 |
commit | a43380e3d5637b5d2e23b001a5c2519696a21c5d (patch) | |
tree | 07db5c4f9432a8e2a85733b6ae263a1f4f83cdc6 /src/southbridge/intel | |
parent | debb8085c6869caaa83cf80d35e035cb9e97ddce (diff) |
pciexp_device: Fix a bug in pciexp_enable_ltr()
'parent_cap' should be found from 'parent' instead of 'dev'.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I99dab83d90287ca924d30dc4aeac0ff96e877e5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
0 files changed, 0 insertions, 0 deletions