diff options
| author | Nico Huber <nico.h@gmx.de> | 2018-11-14 00:00:35 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-01-06 15:54:19 +0000 |
| commit | 9faae2b939d0c83632baeefe80bef1739e125018 (patch) | |
| tree | a3d62f5f14994f1facc2389d189796a836bd8e81 /src/southbridge/intel | |
| parent | d2f678d3bd6ca4c05fa5c652d6cdf4623543e576 (diff) | |
Kconfig: Unify power-after-failure options
The newest and most useful incarnation was hiding in soc/intel/common/.
We move it into the Mainboard menu and extend it with various flags to
be selected to control the default and which options are visible. Also
add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the
boolean to int conversion into Kconfig:
0 - S5
1 - S0
2 - previous state
This patch focuses on the Kconfig code. The C code could be unified as
well, e.g. starting with a common enum and safe wrapper around the
get_option() call.
TEST=Did what-jenkins-does with and without this commit and compared
binaries. Nothing changed for the default configurations.
Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/intel')
24 files changed, 21 insertions, 45 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index d3da239321..e13c666024 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -181,7 +181,7 @@ static void pch_power_options(struct device *dev) /* Get the chip configuration */ config_t *config = dev->chip_info; - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; /* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index ba53f68423..6a96277844 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -29,6 +29,8 @@ config HAVE_INTEL_CHIPSET_LOCKDOWN config SOUTHBRIDGE_INTEL_COMMON_SMM def_bool n + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE config SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT bool diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h index 2076a3d2c1..7f07a724a3 100644 --- a/src/southbridge/intel/common/pmutil.h +++ b/src/southbridge/intel/common/pmutil.h @@ -45,10 +45,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - #define PM1_STS 0x00 #define WAK_STS (1 << 15) #define PCIEXPWAK_STS (1 << 14) diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 6347ad663b..4525934970 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -112,7 +112,7 @@ static void southbridge_smi_sleep(void) u8 reg8; u32 reg32; u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; // save and recover RTC port values u8 tmp70, tmp72; diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index 02e410d8e7..1af57b6917 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -80,10 +80,6 @@ void rangeley_sb_early_initialization(void); #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - #define SOC_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCIE_DEV_SLOT0 1 #define PCIE_DEV_SLOT1 2 diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 827f6bb0f6..5670e162cf 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -22,6 +22,8 @@ config SOUTHBRIDGE_INTEL_I82801DX select HAVE_USBDEBUG select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE if SOUTHBRIDGE_INTEL_I82801DX diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 8c7da55ff1..678d5d78b9 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -45,10 +45,6 @@ int smbus_read_byte(unsigned device, unsigned address); #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - /* * 000 = Non-combined. P0 is primary master. P1 is secondary master. * 001 = Non-combined. P0 is secondary master. P1 is primary master. diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 925251da2a..3c74e98f59 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -103,7 +103,7 @@ static void i82801dx_power_options(struct device *dev) u32 reg32; const char *state; - int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; /* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index b2b4662f60..e7a9589116 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -276,7 +276,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat * CMOS or even better from GNVS. Right now it's hard * coded at compile time. */ - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; /* First, disable further SMIs */ reg8 = inb(pmbase + SMI_EN); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 40c2bb72e3..29c8736552 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -58,10 +58,6 @@ int southbridge_detect_s3_resume(void); #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index c16b8a6649..e8cfc74ac1 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -172,7 +172,7 @@ static void i82801gx_power_options(struct device *dev) /* Get the chip configuration */ config_t *config = dev->chip_info; - int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; /* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index aed1999054..f094ed8920 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -85,11 +85,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - - /* D31:F0 LPC bridge */ #define D31F0_PMBASE 0x40 #define D31F0_ACPI_CNTL 0x44 diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index b809a4e3b7..dd37a0bd74 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -170,7 +170,7 @@ static void i82801ix_power_options(struct device *dev) /* Get the chip configuration */ config_t *config = dev->chip_info; - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; /* BIOS must program... */ diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index b215812601..2bc18fa8fe 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -30,6 +30,8 @@ config SOUTHBRIDGE_INTEL_I82801JX select COMMON_FADT select SOUTHBRIDGE_INTEL_COMMON_SMM select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE if SOUTHBRIDGE_INTEL_I82801JX diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 3c09746f81..4813dd83b3 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -76,11 +76,6 @@ #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - - /* D31:F0 LPC bridge */ #define D31F0_PMBASE 0x40 #define PMBASE D31F0_PMBASE diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 2ff2acd095..0f82f90455 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -172,7 +172,7 @@ static void i82801jx_power_options(struct device *dev) /* Get the chip configuration */ config_t *config = dev->chip_info; - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; /* BIOS must program... */ diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 7e2254e4d1..bb6e22cb73 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -38,6 +38,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy select INTEL_DESCRIPTOR_MODE_CAPABLE select SOUTHBRIDGE_INTEL_COMMON_GPIO select HAVE_INTEL_CHIPSET_LOCKDOWN + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE config EHCI_BAR hex diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 24a217d284..3358633792 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -174,7 +174,7 @@ static void pch_power_options(struct device *dev) /* Get the chip configuration */ config_t *config = dev->chip_info; - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; /* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 35bf0caced..19add778f3 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -82,10 +82,6 @@ void southbridge_configure_default_intmap(void); #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index e510f19b6c..d305635398 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -403,7 +403,7 @@ static void southbridge_smi_sleep(void) u8 reg8; u32 reg32; u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; // save and recover RTC port values u8 tmp70, tmp72; diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index e11bcef818..79f30ae706 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -39,6 +39,8 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select HAVE_INTEL_CHIPSET_LOCKDOWN select COMMON_FADT + select HAVE_POWER_STATE_AFTER_FAILURE + select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE config INTEL_LYNXPOINT_LP bool diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 5b48da0848..10f57f543e 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -189,7 +189,7 @@ static void pch_power_options(struct device *dev) /* Get the chip configuration */ config_t *config = dev->chip_info; u16 pmbase = get_pmbase(); - int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE; int nmi_option; /* Which state do we want to goto after g3 (power restored)? diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index ee041d9dd2..2aa6b48785 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -210,10 +210,6 @@ void mainboard_config_superio(void); #define MAINBOARD_POWER_ON 1 #define MAINBOARD_POWER_KEEP 2 -#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON -#endif - /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 72298f3d91..fd1ba228a6 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -111,7 +111,7 @@ static void southbridge_smi_sleep(void) u8 reg8; u32 reg32; u8 slp_typ; - u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE; u16 pmbase = get_pmbase(); // save and recover RTC port values |