intel/i945 intel/i82801gx: remove explicit pcie config accesses

Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.

Change-Id: I46e69154cf576ddb642c34b6dd2bc0d27cc19b7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3811
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

4 files changed, 24 insertions, 27 deletions

diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c
index ad9faa5a9f..96e662c638 100644
--- a/src/southbridge/intel/i82801gx/azalia.c
+++ b/src/southbridge/intel/i82801gx/azalia.c
@@ -224,39 +224,35 @@ static void azalia_init(struct device *dev)
 	u8 reg8;
 	u32 reg32;
 
-#if CONFIG_MMCONF_SUPPORT
 	// ESD
-	reg32 = pci_mmio_read_config32(dev, 0x134);
+	reg32 = pci_read_config32(dev, 0x134);
 	reg32 &= 0xff00ffff;
 	reg32 |= (2 << 16);
-	pci_mmio_write_config32(dev, 0x134, reg32);
+	pci_write_config32(dev, 0x134, reg32);
 
 	// Link1 description
-	reg32 = pci_mmio_read_config32(dev, 0x140);
+	reg32 = pci_read_config32(dev, 0x140);
 	reg32 &= 0xff00ffff;
 	reg32 |= (2 << 16);
-	pci_mmio_write_config32(dev, 0x140, reg32);
+	pci_write_config32(dev, 0x140, reg32);
 
 	// Port VC0 Resource Control Register
-	reg32 = pci_mmio_read_config32(dev, 0x114);
+	reg32 = pci_read_config32(dev, 0x114);
 	reg32 &= 0xffffff00;
 	reg32 |= 1;
-	pci_mmio_write_config32(dev, 0x114, reg32);
+	pci_write_config32(dev, 0x114, reg32);
 
 	// VCi traffic class
-	reg8 = pci_mmio_read_config8(dev, 0x44);
+	reg8 = pci_read_config8(dev, 0x44);
 	reg8 |= (7 << 0); // TC7
-	pci_mmio_write_config8(dev, 0x44, reg8);
+	pci_write_config8(dev, 0x44, reg8);
 
 	// VCi Resource Control
-	reg32 = pci_mmio_read_config32(dev, 0x120);
+	reg32 = pci_read_config32(dev, 0x120);
 	reg32 |= (1 << 31);
 	reg32 |= (1 << 24); // VCi ID
 	reg32 |= (0x80 << 0); // VCi map
-	pci_mmio_write_config32(dev, 0x120, reg32);
-#else
-#error ICH7 Azalia required CONFIG_MMCONF_SUPPORT
-#endif
+	pci_write_config32(dev, 0x120, reg32);
 
 	/* Set Bus Master */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c
index 7fe14bdd34..ed5921b356 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.c
+++ b/src/southbridge/intel/i82801gx/i82801gx.c
@@ -23,6 +23,10 @@
 #include <device/pci.h>
 #include "i82801gx.h"
 
+#if !CONFIG_MMCONF_SUPPORT_DEFAULT
+#error ICH7 requires CONFIG_MMCONF_SUPPORT_DEFAULT
+#endif
+
 void i82801gx_enable(device_t dev)
 {
 	u32 reg32;
diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c
index 1bc1bed523..0825dec67f 100644
--- a/src/southbridge/intel/i82801gx/pcie.c
+++ b/src/southbridge/intel/i82801gx/pcie.c
@@ -55,20 +55,17 @@ static void pci_init(struct device *dev)
 	reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
 	pci_write_config32(dev, 0xe1, reg32);
 
-#if CONFIG_MMCONF_SUPPORT
 	/* Set VC0 transaction class */
-	reg32 = pci_mmio_read_config32(dev, 0x114);
+	reg32 = pci_read_config32(dev, 0x114);
 	reg32 &= 0xffffff00;
 	reg32 |= 1;
-	pci_mmio_write_config32(dev, 0x114, reg32);
+	pci_write_config32(dev, 0x114, reg32);
 
 	/* Mask completion timeouts */
-	reg32 = pci_mmio_read_config32(dev, 0x148);
+	reg32 = pci_read_config32(dev, 0x148);
 	reg32 |= (1 << 14);
-	pci_mmio_write_config32(dev, 0x148, reg32);
-#else
-#error "MMIO needed for ICH7 PCIe"
-#endif
+	pci_write_config32(dev, 0x148, reg32);
+
 	/* Enable common clock configuration */
 	// Are there cases when we don't want that?
 	reg16 = pci_read_config16(dev, 0x50);
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index 03c5d0912c..ba4d0148e4 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -319,13 +319,13 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
 		/* Always set the flag in case CMOS was changed on runtime. For
 		 * "KEEP", switch to "OFF" - KEEP is software emulated
 		 */
-		reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+		reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
 		if (s5pwr == MAINBOARD_POWER_ON) {
 			reg8 &= ~1;
 		} else {
 			reg8 |= 1;
 		}
-		pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
+		pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
 
 		/* also iterates over all bridges on bus 0 */
 		busmaster_disable_on_bus(0);
@@ -494,7 +494,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
 	if (tco_sts & (1 << 8)) { // BIOSWR
 		u8 bios_cntl;
 
-		bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
+		bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
 
 		if (bios_cntl & 1) {
 			/* BWE is RW, so the SMI was caused by a
@@ -508,7 +508,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_
 			 * box.
 			 */
 			printk(BIOS_DEBUG, "Switching back to RO\n");
-			pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
+			pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
 		} /* No else for now? */
 	} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
 		/* Handle TCO timeout */
@@ -635,7 +635,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
 	u32 smi_sts;
 
 	/* Update global variable pmbase */
-	pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+	pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
 
 	/* We need to clear the SMI status registers, or we won't see what's
 	 * happening in the following calls.