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authorUwe Hermann <uwe@hermann-uwe.de>2010-11-18 20:12:13 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-11-18 20:12:13 +0000
commit607614d0a9cb589c914d92c1b8957b8141dcaf8e (patch)
tree76cd959e4051eafe99a8fc2b9fbd27c85acdbb93 /src/southbridge/intel
parent24f324cb855b77db17b543feed72a03da0e06bc6 (diff)
Fix/drop some obsolete comments,
- s/Options.lb/devicetree.cb/ - s/Config.lb/devicetree.cb/ - s/cache_as_ram_auto.c/romstage.c/ - h8dmr_fam10/README: Drop obsolete comment, we have mc_patch_01000086.h in the tree now. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/i82801ax/i82801ax_lpc.c2
-rw-r--r--src/southbridge/intel/i82801bx/i82801bx_lpc.c2
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_ide.c2
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_sata.c2
-rw-r--r--src/southbridge/intel/i82870/p64h2_ioapic.c6
5 files changed, 7 insertions, 7 deletions
diff --git a/src/southbridge/intel/i82801ax/i82801ax_lpc.c b/src/southbridge/intel/i82801ax/i82801ax_lpc.c
index 46878f8dce..c9404ed3c0 100644
--- a/src/southbridge/intel/i82801ax/i82801ax_lpc.c
+++ b/src/southbridge/intel/i82801ax/i82801ax_lpc.c
@@ -68,7 +68,7 @@ typedef struct southbridge_intel_i82801ax_config config_t;
/*
* Use 0x0ef8 for a bitmap to cover all these IRQ's.
* Use the defined IRQ values above or set mainboard
- * specific IRQ values in your mainboards Config.lb.
+ * specific IRQ values in your devicetree.cb.
*/
static void i82801ax_enable_apic(struct device *dev)
{
diff --git a/src/southbridge/intel/i82801bx/i82801bx_lpc.c b/src/southbridge/intel/i82801bx/i82801bx_lpc.c
index c379428c86..0ff44e6054 100644
--- a/src/southbridge/intel/i82801bx/i82801bx_lpc.c
+++ b/src/southbridge/intel/i82801bx/i82801bx_lpc.c
@@ -70,7 +70,7 @@ typedef struct southbridge_intel_i82801bx_config config_t;
/*
* Use 0x0ef8 for a bitmap to cover all these IRQ's.
* Use the defined IRQ values above or set mainboard
- * specific IRQ values in your mainboards Config.lb.
+ * specific IRQ values in your devicetree.cb.
*/
static void i82801bx_enable_apic(struct device *dev)
{
diff --git a/src/southbridge/intel/i82801gx/i82801gx_ide.c b/src/southbridge/intel/i82801gx/i82801gx_ide.c
index 84b50d6535..6e05e0d9b5 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_ide.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_ide.c
@@ -37,7 +37,7 @@ static void ide_init(struct device *dev)
printk(BIOS_DEBUG, "i82801gx_ide: initializing... ");
if (config == NULL) {
- printk(BIOS_ERR, "\ni82801gx_ide: Not mentioned in mainboard's Config.lb!\n");
+ printk(BIOS_ERR, "\ni82801gx_ide: Not mentioned in devicetree.cb!\n");
// Trying to set somewhat safe defaults instead of bailing out.
enable_primary = enable_secondary = 1;
} else {
diff --git a/src/southbridge/intel/i82801gx/i82801gx_sata.c b/src/southbridge/intel/i82801gx/i82801gx_sata.c
index a5be98735c..c3908489eb 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_sata.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_sata.c
@@ -36,7 +36,7 @@ static void sata_init(struct device *dev)
printk(BIOS_DEBUG, "i82801gx_sata: initializing...\n");
if (config == NULL) {
- printk(BIOS_ERR, "i82801gx_sata: error: device not in Config.lb!\n");
+ printk(BIOS_ERR, "i82801gx_sata: error: device not in devicetree.cb!\n");
return;
}
diff --git a/src/southbridge/intel/i82870/p64h2_ioapic.c b/src/southbridge/intel/i82870/p64h2_ioapic.c
index 8af57beed7..6a0f0d222f 100644
--- a/src/southbridge/intel/i82870/p64h2_ioapic.c
+++ b/src/southbridge/intel/i82870/p64h2_ioapic.c
@@ -40,10 +40,10 @@ static void p64h2_ioapic_init(device_t dev)
// A note on IOAPIC addresses:
// 0 and 1 are used for the local APICs of the dual virtual
- // (hyper-threaded) CPUs of physical CPU 0 (mainboard/Config.lb).
+ // (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb).
// 6 and 7 are used for the local APICs of the dual virtual
- // (hyper-threaded) CPUs of physical CPU 1 (mainboard/Config.lb).
- // 2 is used for the IOAPIC in the 82801 Southbridge (hard-coded in i82801xx_lpc.c)
+ // (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb).
+ // 2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c)
// Map APIC index into APIC ID
// IDs 3, 4, 5, and 8+ are available (see above note)