diff options
author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-01-18 04:25:48 +0200 |
---|---|---|
committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-11-28 10:05:28 +0000 |
commit | 560c3f5ccfff0fc289bb46f1b1b6c4236817590a (patch) | |
tree | 59906cc1926d7e643dd1ec95022c87228560f152 /src/southbridge/intel | |
parent | 0c745347d09e08d9cf388600558ea41634e5cbcd (diff) |
aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG
Both SMM_ASEG and SMM_TSEG choices work.
There is periodic TCO timeout occurring.
At least with DEBUG_SMI kernel reports low memory corruption.
Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r-- | src/southbridge/intel/i82801dx/Kconfig | 2 | ||||
-rw-r--r-- | src/southbridge/intel/i82801dx/Makefile.inc | 2 | ||||
-rw-r--r-- | src/southbridge/intel/i82801dx/fadt.c | 21 | ||||
-rw-r--r-- | src/southbridge/intel/i82801dx/i82801dx.h | 4 | ||||
-rw-r--r-- | src/southbridge/intel/i82801dx/lpc.c | 12 | ||||
-rw-r--r-- | src/southbridge/intel/i82801dx/smihandler.c | 12 |
6 files changed, 34 insertions, 19 deletions
diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index 98c1a477ff..391a59fc6b 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -3,7 +3,9 @@ config SOUTHBRIDGE_INTEL_I82801DX bool select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_SMM select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RTC select SOUTHBRIDGE_INTEL_COMMON_RESET diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index be17cf9920..5db45379fe 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -15,4 +15,6 @@ ramstage-y += lpc.c ramstage-y += usb.c ramstage-y += usb2.c +smm-y += smihandler.c + endif diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c index e12b2cae1f..fdb7fb33a7 100644 --- a/src/southbridge/intel/i82801dx/fadt.c +++ b/src/southbridge/intel/i82801dx/fadt.c @@ -1,20 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <device/pci_ops.h> #include <acpi/acpi.h> -#include <version.h> - -/* FIXME: This needs to go into a separate .h file - * to be included by the ich7 smi handler, ich7 smi init - * code and the mainboard fadt. - */ -#define APM_CNT 0x0 /* ACPI mode only */ -#define CST_CONTROL 0x85 -#define PST_CONTROL 0x0 -#define ACPI_DISABLE 0xAA -#define ACPI_ENABLE 0x55 -#define S4_BIOS 0x77 -#define GNVS_UPDATE 0xea +#include <cpu/x86/smm.h> +#include <device/pci_ops.h> void acpi_fill_fadt(acpi_fadt_t *fadt) { @@ -24,9 +12,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = ACPI_ENABLE; - fadt->acpi_disable = ACPI_DISABLE; - fadt->pstate_cnt = PST_CONTROL; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; } fadt->pm1a_evt_blk = pmbase; diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index ecb992471e..4c1366e8c5 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -140,8 +140,8 @@ void i82801dx_lpc_setup(void); #define DEVACT_STS 0x44 #define SS_CNT 0x50 -#define TCOBASE 0x60 /* TCO Base Address Register */ -#define TCO1_CNT 0x08 /* TCO1 Control Register */ +/* TCO1 Control Register */ +#define TCO1_CNT 0x68 #define GEN_PMCON_1 0xa0 #define GEN_PMCON_2 0xa2 diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index c92562aaed..d914335c34 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -4,6 +4,7 @@ #include <arch/io.h> #include <arch/ioapic.h> #include <console/console.h> +#include <cpu/x86/smm.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -162,6 +163,15 @@ static void i82801dx_rtc_init(struct device *dev) pci_write_config8(dev, RTC_CONF, 0x04); } +static void i82801dx_set_acpi_mode(struct device *dev) +{ + if (!acpi_is_wakeup_s3()) { + apm_control(APM_CNT_ACPI_DISABLE); + } else { + apm_control(APM_CNT_ACPI_ENABLE); + } +} + static void i82801dx_lpc_route_dma(struct device *dev, u8 mask) { u16 reg16; @@ -240,6 +250,8 @@ static void lpc_init(struct device *dev) enable_hpet(dev); setup_i8259(); + + i82801dx_set_acpi_mode(dev); } static void i82801dx_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c new file mode 100644 index 0000000000..050567a11c --- /dev/null +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/pmutil.h> +#include "i82801dx.h" + +void southbridge_smi_monitor(void) +{ +} + +void southbridge_finalize_all(void) +{ +} |