diff options
| author | Keith Hui <buurin@gmail.com> | 2024-04-15 17:36:30 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-04-18 10:58:19 +0000 |
| commit | 4da9b9f0a9947eef5a682c42f107502306414a43 (patch) | |
| tree | 279a8356dceab8738475c56857447af24939c600 /src/southbridge/intel | |
| parent | b93d6676d379897d4fdde630fc36d667036f8c8a (diff) | |
sb/intel/bd82x6x/pch.asl: Break out GPIO blink field
Break out the individual bits of GPIO blink register as was done
for GPIO level register. An upcoming patch will use this.
Change-Id: I6f4749f60a9d569deba4b31f09f07a1321dabf4a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81922
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/pch.asl | 36 |
1 files changed, 32 insertions, 4 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 718d79ed82..5d74261e5b 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -97,10 +97,38 @@ Scope(\) GP30, 1, GP31, 1, Offset(0x18), // GPIO Blink - GB00, 8, - GB01, 8, - GB02, 8, - GB03, 8, + GB00, 1, + GB01, 1, + GB02, 1, + GB03, 1, + GB04, 1, + GB05, 1, + GB06, 1, + GB07, 1, + GB08, 1, + GB09, 1, + GB10, 1, + GB11, 1, + GB12, 1, + GB13, 1, + GB14, 1, + GB15, 1, + GB16, 1, + GB17, 1, + GB18, 1, + GB19, 1, + GB20, 1, + GB21, 1, + GB22, 1, + GB23, 1, + GB24, 1, + GB25, 1, + GB26, 1, + GB27, 1, + GB28, 1, + GB29, 1, + GB30, 1, + GB31, 1, Offset(0x2c), // GPIO Invert GIV0, 8, GIV1, 8, |