diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-03-24 15:06:17 +0100 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2019-04-13 14:49:31 +0000 |
| commit | 425e75a2db999d65400b49ebe65ae26c64aabcd9 (patch) | |
| tree | b2407f1d50cc8a6129f226d7df919afcd2fd89f7 /src/southbridge/intel | |
| parent | a3caa2d3bbe791c39af2b56ae6f94ec83c4e09e2 (diff) | |
sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
Use common code to detect ACPI S3.
Tested on Thinkpad X60.
Change-Id: Ia759a9ed141efc8130860300f2a8961f0c084d70
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/i82801gx/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/early_lpc.c | 43 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 1 |
4 files changed, 2 insertions, 45 deletions
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index d4615faf7d..a7d65c52bb 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -25,6 +25,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select HAVE_INTEL_CHIPSET_LOCKDOWN select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select INTEL_HAS_TOP_SWAP diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 290794b08d..b72ca235f5 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -34,6 +34,6 @@ ramstage-y += watchdog.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -romstage-y += early_smbus.c early_lpc.c +romstage-y += early_smbus.c endif diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c deleted file mode 100644 index a52fb8512e..0000000000 --- a/src/southbridge/intel/i82801gx/early_lpc.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <arch/acpi.h> -#include "i82801gx.h" - -int southbridge_detect_s3_resume(void) -{ - u32 reg32; - - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - if (!acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - return 1; - } - } - - return 0; -} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 1e7dfdb809..3db5d49f3f 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -48,7 +48,6 @@ int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); -int southbridge_detect_s3_resume(void); #endif #endif |