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authorRonald G. Minnich <rminnich@gmail.com>2009-10-09 20:07:48 +0000
committerRonald G. Minnich <rminnich@gmail.com>2009-10-09 20:07:48 +0000
commit42584096c30440ecef1c50322f2f39ccbc9e5230 (patch)
treea0299ad6741f27a22af19adad4978aae4bca8df5 /src/southbridge/intel
parent517bb208dcb2739108d07357c79e78ecd474523f (diff)
This change allows us to see the spd on the s850, finally.
There is an i2c mux out there. We found it using a user level program that, as usual, began by inverting all gpios until we found out what we needed to know. In the end, we just set up the GPIOs as the factory bios does. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/i82801er/i82801er_early_smbus.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801er/i82801er_early_smbus.c b/src/southbridge/intel/i82801er/i82801er_early_smbus.c
index 3e051a2cab..42a55680af 100644
--- a/src/southbridge/intel/i82801er/i82801er_early_smbus.c
+++ b/src/southbridge/intel/i82801er/i82801er_early_smbus.c
@@ -9,6 +9,7 @@ static void enable_smbus(void)
print_spew("SMBus controller enabled\r\n");
pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
+ print_debug_hex32(pci_read_config32(dev, 0x20));
/* Set smbus enable */
pci_write_config8(dev, 0x40, 1);
/* Set smbus iospace enable */