diff options
| author | Kevin Paul Herbert <kph@meraki.net> | 2015-02-25 00:36:51 -0800 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-02-27 18:15:33 +0100 |
| commit | 4104e6cd30ba80f93e764e5036f79dd7a60d5b1c (patch) | |
| tree | bf50e439a9c1c84692c81876f3012796cb3221cc /src/southbridge/intel | |
| parent | c684d05b0fa66f86b3c94ecd46388858d8e5dcaa (diff) | |
x86: Fix pointer arithmetic regressions from MMIO changes
During the development of commit bde6d30 (x86: Change MMIO addr
in readN(addr)/writeN(addr, val) to pointer), there were several iterations
and patterns tried. An intermediate pattern was the use of u32 pointers,
and division by sizeof(u32). Some of these did not get properly
changed to pointer types of length 1, causing a regression in
the Intel Ibex Peak SATA driver, fixed in commit 9b5f137
(Intel ibexpeak: Fix SATA configuration).
Other regressions of this pattern are fixed here. I audited all changes
to u32 types, and the other ones are safe.
Change-Id: I9e73ac8f4329df8bf0cdd1a14759f0280f974052
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Reviewed-on: http://review.coreboot.org/8530
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/lpc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 8f2967048a..80673a627d 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -52,7 +52,7 @@ static void soc_enable_apic(struct device *dev) u32 reg32; volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - u32 *ilb_base = (u32 *)(pci_read_config32(dev, IBASE) & ~0x0f); + u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f); /* * Enable ACPI I/O and power management. |