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authorKyösti Mälkki <kyosti.malkki@gmail.com>2023-04-17 15:20:40 +0300
committerFelix Held <felix-coreboot@felixheld.de>2023-04-29 01:20:54 +0000
commit240baa31e8a804029069e21f523556d8628f6001 (patch)
tree1d58b857233bb5029da1ac99e11c86d911618a25 /src/southbridge/intel
parent097f5404607ea548cc49feb82bd99663c1ada0fe (diff)
ACPI: Make FADT entries for RTC/CMOS architectural
For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY that points to same offset. Since the century field inside RTC falls within the NVRAM space, and could interfere with OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY. There were no reference for the use of offset 0x48 for century. Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/fadt.c2
-rw-r--r--src/southbridge/intel/i82371eb/fadt.c3
-rw-r--r--src/southbridge/intel/i82801dx/fadt.c2
-rw-r--r--src/southbridge/intel/i82801gx/fadt.c3
-rw-r--r--src/southbridge/intel/i82801ix/fadt.c3
-rw-r--r--src/southbridge/intel/i82801jx/fadt.c3
-rw-r--r--src/southbridge/intel/ibexpeak/fadt.c2
-rw-r--r--src/southbridge/intel/lynxpoint/fadt.c2
8 files changed, 4 insertions, 16 deletions
diff --git a/src/southbridge/intel/bd82x6x/fadt.c b/src/southbridge/intel/bd82x6x/fadt.c
index e76682d1cb..b0d719f54d 100644
--- a/src/southbridge/intel/bd82x6x/fadt.c
+++ b/src/southbridge/intel/bd82x6x/fadt.c
@@ -25,8 +25,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
- fadt->day_alrm = 0xd;
- fadt->mon_alrm = 0x00;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
fadt->flags |= ACPI_FADT_WBINVD |
diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c
index 00e204ebef..43e119b746 100644
--- a/src/southbridge/intel/i82371eb/fadt.c
+++ b/src/southbridge/intel/i82371eb/fadt.c
@@ -31,8 +31,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
fadt->duty_width = 3; /* this width is in bits */
- fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */
- fadt->mon_alrm = 0x0; /* not supported */
+
/*
* bit meaning
* 0 1: We have user-visible legacy devices
diff --git a/src/southbridge/intel/i82801dx/fadt.c b/src/southbridge/intel/i82801dx/fadt.c
index e5ad336709..56c3cc7fdb 100644
--- a/src/southbridge/intel/i82801dx/fadt.c
+++ b/src/southbridge/intel/i82801dx/fadt.c
@@ -19,8 +19,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 8;
- fadt->day_alrm = 0xd;
- fadt->mon_alrm = 0x00;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c
index ccbc504f20..0da488db07 100644
--- a/src/southbridge/intel/i82801gx/fadt.c
+++ b/src/southbridge/intel/i82801gx/fadt.c
@@ -33,8 +33,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->duty_width = 3;
else
fadt->duty_width = 0;
- fadt->day_alrm = 0xd;
- fadt->mon_alrm = 0x00;
+
fadt->iapc_boot_arch = ACPI_FADT_8042 | ACPI_FADT_LEGACY_DEVICES;
fadt->flags |= (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED
| ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE
diff --git a/src/southbridge/intel/i82801ix/fadt.c b/src/southbridge/intel/i82801ix/fadt.c
index bcd7d900a0..ee861fd0ec 100644
--- a/src/southbridge/intel/i82801ix/fadt.c
+++ b/src/southbridge/intel/i82801ix/fadt.c
@@ -26,8 +26,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->p_lvl3_lat = 0x39;
fadt->duty_offset = 1;
fadt->duty_width = 3;
- fadt->day_alrm = 0xd;
- fadt->mon_alrm = 0x00;
+
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE;
fadt->flags |= ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE |
diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c
index 73d7ea017c..ca5dfebbd9 100644
--- a/src/southbridge/intel/i82801jx/fadt.c
+++ b/src/southbridge/intel/i82801jx/fadt.c
@@ -26,8 +26,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->p_lvl3_lat = 0; /* FIXME: Is this correct? */
fadt->duty_offset = 1;
fadt->duty_width = 0;
- fadt->day_alrm = 0xd;
- fadt->mon_alrm = 0x00;
+
fadt->iapc_boot_arch = ACPI_FADT_8042 | ACPI_FADT_LEGACY_DEVICES;
fadt->flags |= (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED
| ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE
diff --git a/src/southbridge/intel/ibexpeak/fadt.c b/src/southbridge/intel/ibexpeak/fadt.c
index d750890c54..44ee59a06f 100644
--- a/src/southbridge/intel/ibexpeak/fadt.c
+++ b/src/southbridge/intel/ibexpeak/fadt.c
@@ -25,8 +25,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->pm_tmr_len = 4;
fadt->gpe0_blk_len = 16;
- fadt->day_alrm = 0xd;
- fadt->mon_alrm = 0x00;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
fadt->flags |= ACPI_FADT_WBINVD |
diff --git a/src/southbridge/intel/lynxpoint/fadt.c b/src/southbridge/intel/lynxpoint/fadt.c
index eaea091257..d83c58fa29 100644
--- a/src/southbridge/intel/lynxpoint/fadt.c
+++ b/src/southbridge/intel/lynxpoint/fadt.c
@@ -37,8 +37,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
else
fadt->gpe0_blk_len = 2 * 8;
- fadt->day_alrm = 0xd;
- fadt->mon_alrm = 0x00;
fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
fadt->flags |= ACPI_FADT_WBINVD |