kbuild: automatically include southbridges

This change switches all southbridge vendors and southbridges
to be autoincluded by Makefile.inc, rather than having to be
mentioned explicitly in southbridge/Makefile.inc or in
southbridge/<vendor>/Makefile.inc.

In order to be able to drop southbridge/amd/Makefile.inc, some
scattered source files had to be moved to a southbridge/amd/common
directory, in accordance to what we are doing on other architectures
already.

This means, vendor and southbridge directories are now "drop
in", e.g. be placed in the coreboot directory hierarchy
without having to modify any higher level coreboot files.

The long term plan is to enable out of tree components to be
built with a given coreboot version (given that the API did not
change).

Change-Id: I79bd644a0a3c4e8320c80f8cc7a7f8ffd65d32f2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/9796
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

19 files changed, 72 insertions, 19 deletions

diff --git a/src/southbridge/intel/Makefile.inc b/src/southbridge/intel/Makefile.inc
deleted file mode 100644
index dd20d46b06..0000000000
--- a/src/southbridge/intel/Makefile.inc
+++ /dev/null
@@ -1,19 +0,0 @@
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON) += common
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_ESB6300) += esb6300
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I3100) += i3100
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82371EB) += i82371eb
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801AX) += i82801ax
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801BX) += i82801bx
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801CX) += i82801cx
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801DX) += i82801dx
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801EX) += i82801ex
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) += i82801gx
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82801IX) += i82801ix
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82870) += i82870
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_SCH) += sch
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += bd82x6x
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += bd82x6x
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK) += ibexpeak
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT) += lynxpoint
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X) += fsp_bd82x6x
-subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_rangeley
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index 83de051d51..234c009716 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -17,6 +17,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_C216)$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X),y)
+
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS
@@ -107,3 +109,5 @@ else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
 endif
 
 PHONY += bd82x6x_add_me
+
+endif
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc
index 4374ebcb43..5c613ebb4c 100644
--- a/src/southbridge/intel/common/Makefile.inc
+++ b/src/southbridge/intel/common/Makefile.inc
@@ -17,5 +17,9 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y)
+
 romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c
 ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
+
+endif
diff --git a/src/southbridge/intel/esb6300/Makefile.inc b/src/southbridge/intel/esb6300/Makefile.inc
index bb70fdcc62..fba8c2310b 100644
--- a/src/southbridge/intel/esb6300/Makefile.inc
+++ b/src/southbridge/intel/esb6300/Makefile.inc
@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_ESB6300),y)
+
 ramstage-y += esb6300.c
 ramstage-y += reset.c
 ramstage-y += uhci.c
@@ -10,3 +12,5 @@ ramstage-y += pci.c
 ramstage-y += pic.c
 ramstage-y += bridge1c.c
 ramstage-y += ac97.c
+
+endif
diff --git a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc
index 208611b716..1bfed232d8 100644
--- a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc
@@ -18,6 +18,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X),y)
+
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS
@@ -71,3 +73,5 @@ endif
 PHONY += bd82x6x_add_me
 
 CPPFLAGS_common += -I$(src)/southbridge/intel/fsp_bd82x6x
+
+endif
diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc
index 48ac522ddd..1d3305288b 100644
--- a/src/southbridge/intel/fsp_rangeley/Makefile.inc
+++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc
@@ -18,6 +18,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y)
+
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS
@@ -48,3 +50,5 @@ rangeley_add_descriptor: $(obj)/coreboot.pre $(IFDTOOL)
 endif
 
 PHONY += rangeley_add_descriptor
+
+endif
diff --git a/src/southbridge/intel/i3100/Makefile.inc b/src/southbridge/intel/i3100/Makefile.inc
index dc3d0395e9..bcc6d06171 100644
--- a/src/southbridge/intel/i3100/Makefile.inc
+++ b/src/southbridge/intel/i3100/Makefile.inc
@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I3100),y)
+
 ramstage-y += i3100.c
 ramstage-y += uhci.c
 ramstage-y += lpc.c
@@ -8,3 +10,5 @@ ramstage-y += pci.c
 ramstage-y += ioapic.c
 ramstage-y += reset.c
 ramstage-y += pciexp_portb.c
+
+endif
diff --git a/src/southbridge/intel/i82371eb/Makefile.inc b/src/southbridge/intel/i82371eb/Makefile.inc
index 0aae455980..0ab2531e70 100644
--- a/src/southbridge/intel/i82371eb/Makefile.inc
+++ b/src/southbridge/intel/i82371eb/Makefile.inc
@@ -18,6 +18,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y)
+
 ramstage-y +=  i82371eb.c
 ramstage-y +=  isa.c
 ramstage-y +=  ide.c
@@ -30,3 +32,5 @@ ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.c
 
 romstage-y += early_pm.c
 romstage-y += early_smbus.c
+
+endif
diff --git a/src/southbridge/intel/i82801ax/Makefile.inc b/src/southbridge/intel/i82801ax/Makefile.inc
index aeb1e54901..48eadf396d 100644
--- a/src/southbridge/intel/i82801ax/Makefile.inc
+++ b/src/southbridge/intel/i82801ax/Makefile.inc
@@ -18,6 +18,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801AX),y)
+
 ramstage-y += i82801ax.c
 ramstage-y += ac97.c
 ramstage-y += ide.c
@@ -30,3 +32,5 @@ ramstage-y += reset.c
 ramstage-y += watchdog.c
 
 romstage-y += early_smbus.c
+
+endif
diff --git a/src/southbridge/intel/i82801bx/Makefile.inc b/src/southbridge/intel/i82801bx/Makefile.inc
index f070f05891..44a2ac8836 100644
--- a/src/southbridge/intel/i82801bx/Makefile.inc
+++ b/src/southbridge/intel/i82801bx/Makefile.inc
@@ -18,6 +18,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801BX),y)
+
 ramstage-y += i82801bx.c
 ramstage-y += ac97.c
 ramstage-y += ide.c
@@ -31,3 +33,5 @@ ramstage-y += reset.c
 ramstage-y += watchdog.c
 
 romstage-y += early_smbus.c
+
+endif
diff --git a/src/southbridge/intel/i82801cx/Makefile.inc b/src/southbridge/intel/i82801cx/Makefile.inc
index c375476d47..ab95982a04 100644
--- a/src/southbridge/intel/i82801cx/Makefile.inc
+++ b/src/southbridge/intel/i82801cx/Makefile.inc
@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801CX),y)
+
 ramstage-y += i82801cx.c
 ramstage-y += usb.c
 ramstage-y += lpc.c
@@ -6,3 +8,5 @@ ramstage-y += ac97.c
 #ramstage-y += nic.c
 ramstage-y += pci.c
 ramstage-y += reset.c
+
+endif
diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc
index e412ef9089..d10383cc5a 100644
--- a/src/southbridge/intel/i82801dx/Makefile.inc
+++ b/src/southbridge/intel/i82801dx/Makefile.inc
@@ -19,6 +19,8 @@
 ## MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801DX),y)
+
 ramstage-y += i82801dx.c
 ramstage-y += ac97.c
 ramstage-y += ide.c
@@ -33,3 +35,5 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
 romstage-y += early_smbus.c
+
+endif
diff --git a/src/southbridge/intel/i82801ex/Makefile.inc b/src/southbridge/intel/i82801ex/Makefile.inc
index fb76a98453..240eaf0517 100644
--- a/src/southbridge/intel/i82801ex/Makefile.inc
+++ b/src/southbridge/intel/i82801ex/Makefile.inc
@@ -1,3 +1,5 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801EX),y)
+
 ramstage-y += i82801ex.c
 ramstage-y += uhci.c
 ramstage-y += lpc.c
@@ -9,3 +11,5 @@ ramstage-y += pci.c
 ramstage-y += ac97.c
 ramstage-y += watchdog.c
 ramstage-y += reset.c
+
+endif
diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc
index 6e4d42e519..fa1721f26f 100644
--- a/src/southbridge/intel/i82801gx/Makefile.inc
+++ b/src/southbridge/intel/i82801gx/Makefile.inc
@@ -17,6 +17,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801GX),y)
+
 ramstage-y += i82801gx.c
 ramstage-y += ac97.c
 ramstage-y += azalia.c
@@ -39,3 +41,5 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 
 romstage-y += early_smbus.c early_lpc.c
+
+endif
diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc
index a6580c4208..19f5bb432a 100644
--- a/src/southbridge/intel/i82801ix/Makefile.inc
+++ b/src/southbridge/intel/i82801ix/Makefile.inc
@@ -18,6 +18,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801IX),y)
+
 ramstage-y += i82801ix.c
 ramstage-y += pci.c
 ramstage-y += lpc.c
@@ -40,3 +42,5 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
 romstage-y += early_init.c
 romstage-y += early_smbus.c
 romstage-y += dmi_setup.c
+
+endif
diff --git a/src/southbridge/intel/i82870/Makefile.inc b/src/southbridge/intel/i82870/Makefile.inc
index 190aa4f1e9..790bd01513 100644
--- a/src/southbridge/intel/i82870/Makefile.inc
+++ b/src/southbridge/intel/i82870/Makefile.inc
@@ -1,3 +1,7 @@
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82870),y)
+
 ramstage-y += ioapic.c
 ramstage-y += pcibridge.c
 #ramstage-y += pci_parity.c
+
+endif
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc
index 393655ddbe..f09db1a03e 100644
--- a/src/southbridge/intel/ibexpeak/Makefile.inc
+++ b/src/southbridge/intel/ibexpeak/Makefile.inc
@@ -17,6 +17,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y)
+
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS
@@ -100,3 +102,5 @@ else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
 endif
 
 PHONY += bd82x6x_add_me
+
+endif
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 3b7663ea04..df68db2473 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -17,6 +17,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)
+
 # Run an intermediate step when producing coreboot.rom
 # that adds additional components to the final firmware
 # image outside of CBFS
@@ -104,3 +106,5 @@ else ifneq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
 endif
 
 PHONY += lynxpoint_add_me
+
+endif
diff --git a/src/southbridge/intel/sch/Makefile.inc b/src/southbridge/intel/sch/Makefile.inc
index 0bdd4759e3..bfdbe04266 100644
--- a/src/southbridge/intel/sch/Makefile.inc
+++ b/src/southbridge/intel/sch/Makefile.inc
@@ -17,6 +17,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 ##
 
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_SCH),y)
+
 ramstage-y += south.c
 ramstage-y += audio.c
 ramstage-y += lpc.c
@@ -39,3 +41,5 @@ cbfs-files-$(CONFIG_HAVE_CMC) += cmc.bin
 cmc.bin-file := $(call strip_quotes,$(CONFIG_CMC_FILE))
 cmc.bin-type := raw
 cmc.bin-position := 0xfffd0000
+
+endif