diff options
| author | Hannah Williams <hannah.williams@dell.com> | 2019-05-16 21:32:54 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-06-05 16:45:35 +0000 |
| commit | 1aac543a7af9e5353becc97853de8b4b1da7d4dd (patch) | |
| tree | 3bf85c792c14c7c48d9e420a6441b6af47e06cb2 /src/southbridge/intel | |
| parent | 1583fcd13fe436e815977f96086412adabcb7dd7 (diff) | |
southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw
outw takes (value, addr) not (addr, value)
Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622
Signed-off-by: Hannah Williams <hannah.williams@dell.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/early_init.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c index 32e3bb5f4f..cec7a318bc 100644 --- a/src/southbridge/intel/fsp_rangeley/early_init.c +++ b/src/southbridge/intel/fsp_rangeley/early_init.c @@ -40,8 +40,8 @@ static void rangeley_setup_bars(void) /* Disable the watchdog reboot and turn off the watchdog timer */ write8((void *)(DEFAULT_PBASE + PMC_CFG), read8((void *)(DEFAULT_PBASE + PMC_CFG)) | NO_REBOOT); // disable reboot on timer trigger - outw(DEFAULT_ABASE + TCO1_CNT, inw(DEFAULT_ABASE + TCO1_CNT) | - TCO_TMR_HALT); // disable watchdog timer + outw(inw(DEFAULT_ABASE + TCO1_CNT) | TCO_TMR_HALT, + DEFAULT_ABASE + TCO1_CNT); // disable watchdog timer printk(BIOS_DEBUG, " done.\n"); |