From 1aac543a7af9e5353becc97853de8b4b1da7d4dd Mon Sep 17 00:00:00 2001 From: Hannah Williams Date: Thu, 16 May 2019 21:32:54 -0700 Subject: southbridge/intel/fsp_rangeley: Fix wrong parameters passed to outw outw takes (value, addr) not (addr, value) Change-Id: I6c00413ce9b9b6a3d5691d71ade2b12b08538622 Signed-off-by: Hannah Williams Reviewed-on: https://review.coreboot.org/c/coreboot/+/32842 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Martin Roth --- src/southbridge/intel/fsp_rangeley/early_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge/intel') diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c index 32e3bb5f4f..cec7a318bc 100644 --- a/src/southbridge/intel/fsp_rangeley/early_init.c +++ b/src/southbridge/intel/fsp_rangeley/early_init.c @@ -40,8 +40,8 @@ static void rangeley_setup_bars(void) /* Disable the watchdog reboot and turn off the watchdog timer */ write8((void *)(DEFAULT_PBASE + PMC_CFG), read8((void *)(DEFAULT_PBASE + PMC_CFG)) | NO_REBOOT); // disable reboot on timer trigger - outw(DEFAULT_ABASE + TCO1_CNT, inw(DEFAULT_ABASE + TCO1_CNT) | - TCO_TMR_HALT); // disable watchdog timer + outw(inw(DEFAULT_ABASE + TCO1_CNT) | TCO_TMR_HALT, + DEFAULT_ABASE + TCO1_CNT); // disable watchdog timer printk(BIOS_DEBUG, " done.\n"); -- cgit v1.2.3