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authorMatt DeVillier <matt.devillier@gmail.com>2018-03-04 01:44:15 -0600
committerPatrick Georgi <pgeorgi@google.com>2018-03-08 19:14:17 +0000
commita51e379eaff3652dc64e23bb0d3784222a38723a (patch)
tree5296bfb357dddedc61f585f3bf36c14b351b6044 /src/southbridge/intel/lynxpoint
parent8a6377ec24c85bc6a18eb9c57045746d2261ce1a (diff)
nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APIC
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX IOMMU and the general IOMMU respectively. These addresses have to be configured in MCHBAR registers and reserved from the OS. GFXVTBAR/VTVC0BAR policy registers set to be consistent with proprietary vendor firmwares on hardware of same platform (2 different vendor firmwares compared, found to be identical). Change-Id: Ib8f2fed9ae08491779e76f7d1ddc1bd3eed45ac7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/24983 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c14
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h7
2 files changed, 19 insertions, 2 deletions
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index a5c2351323..03a77d9b3e 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -51,6 +51,10 @@ static void pch_enable_ioapic(struct device *dev)
{
u32 reg32;
+ /* Assign unique bus/dev/fn for I/O APIC */
+ pci_write_config16(dev, LPC_IBDF,
+ PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
+
/* Enable ACPI I/O range decode */
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
@@ -396,9 +400,15 @@ static void lpt_lp_pm_init(struct device *dev)
RCBA32_OR(0x33c8, (1 << 15));
}
-static void enable_hpet(void)
+static void enable_hpet(struct device *const dev)
{
u32 reg32;
+ size_t i;
+
+ /* Assign unique bus/dev/fn for each HPET */
+ for (i = 0; i < 8; ++i)
+ pci_write_config16(dev, LPC_HnBDF(i),
+ PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
/* Move HPET to default address 0xfed00000 and enable it */
reg32 = RCBA32(HPTC);
@@ -570,7 +580,7 @@ static void lpc_init(struct device *dev)
isa_dma_init();
/* Initialize the High Precision Event Timers, if present. */
- enable_hpet();
+ enable_hpet(dev);
setup_i8259();
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index af9e9542b5..f14a339d7b 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -282,6 +282,8 @@ void pch_enable_lpc(void);
#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */
+#define LPC_IBDF 0x6C /* I/O APIC bus/dev/fn */
+#define LPC_HnBDF(n) (0x70 + n * 2) /* HPET n bus/dev/fn */
#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
@@ -670,6 +672,11 @@ void pch_enable_lpc(void);
#define PCH_DISABLE_MEI1 (1 << 1)
#define PCH_ENABLE_DBDF (1 << 0)
+#define PCH_IOAPIC_PCI_BUS 250
+#define PCH_IOAPIC_PCI_SLOT 31
+#define PCH_HPET_PCI_BUS 250
+#define PCH_HPET_PCI_SLOT 15
+
/* ICH7 PMBASE */
#define PM1_STS 0x00
#define WAK_STS (1 << 15)