arch/x86: Replace some __SMM__ guards

We generally do not guard source in attempts to reduce
the final object sizes, but rely on garbage collection.

Most of the __unused attributes inserted here will be
removed when remaining __SIMPLE_DEVICE__ guards can
be removed.

Change-Id: I2440931fab4f41d7e8249c082e6c9b5a9cd0ef13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36641
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 24 insertions, 18 deletions

diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 429fa42ab1..2df03c9cdc 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -45,9 +45,8 @@
 #include <vendorcode/google/chromeos/gnvs.h>
 #endif
 
-#ifndef __SMM__
 /* Path that the BIOS should take based on ME state */
-static const char *me_bios_path_values[] = {
+static const char *me_bios_path_values[] __unused = {
 	[ME_NORMAL_BIOS_PATH]		= "Normal",
 	[ME_S3WAKE_BIOS_PATH]		= "S3 Wake",
 	[ME_ERROR_BIOS_PATH]		= "Error",
@@ -56,7 +55,6 @@ static const char *me_bios_path_values[] = {
 	[ME_FIRMWARE_UPDATE_BIOS_PATH]	= "Firmware Update",
 };
 static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev);
-#endif
 
 /* MMIO base address for MEI interface */
 static u32 *mei_base_address;
@@ -557,10 +555,8 @@ static int mkhi_global_reset(void)
 }
 #endif
 
-#ifdef __SMM__
-
 /* Send END OF POST message to the ME */
-static int mkhi_end_of_post(void)
+static int __unused mkhi_end_of_post(void)
 {
 	struct mkhi_header mkhi = {
 		.group_id	= MKHI_GROUP_ID_GEN,
@@ -579,6 +575,8 @@ static int mkhi_end_of_post(void)
 	return 0;
 }
 
+#ifdef __SIMPLE_DEVICE__
+
 void intel_me_finalize_smm(void)
 {
 	struct me_hfs hfs;
@@ -619,7 +617,7 @@ void intel_me_finalize_smm(void)
 	RCBA32_OR(FD2, PCH_DISABLE_MEI1);
 }
 
-#else /* !__SMM__ */
+#else /* !__SIMPLE_DEVICE__ */
 
 static inline int mei_sendrecv_icc(struct icc_header *icc,
 				   void *req_data, int req_bytes,
@@ -901,6 +899,8 @@ static const struct pci_driver intel_me __pci_driver = {
 	.devices= pci_device_ids,
 };
 
+#endif /* !__SIMPLE_DEVICE__ */
+
 /******************************************************************************
  *									     */
 static u32 me_to_host_words_pending(void)
@@ -938,7 +938,7 @@ struct mbp_payload {
  * mbp seems to be following its own flow, let's retrieve it in a dedicated
  * function.
  */
-static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
+static int __unused intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
 {
 	mbp_header mbp_hdr;
 	u32 me2host_pending;
@@ -947,7 +947,11 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
 	struct mbp_payload *mbp;
 	int i;
 
+#ifdef __SIMPLE_DEVICE__
+	pci_read_dword_ptr(PCI_BDF(dev), &hfs2, PCI_ME_HFS2);
+#else
 	pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2);
+#endif
 
 	if (!hfs2.mbp_rdy) {
 		printk(BIOS_ERR, "ME: MBP not ready\n");
@@ -1057,8 +1061,10 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
 	return 0;
 
 mbp_failure:
+#ifdef __SIMPLE_DEVICE__
+	intel_me_mbp_give_up(PCI_BDF(dev));
+#else
 	intel_me_mbp_give_up(dev);
+#endif
 	return -1;
 }
-
-#endif /* !__SMM__ */
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index dc7b9580d9..cb50c125ec 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -90,7 +90,7 @@ u16 get_gpiobase(void)
 	return gpiobase;
 }
 
-#ifndef __SMM__
+#ifndef __SIMPLE_DEVICE__
 
 /* Put device in D3Hot Power State */
 static void pch_enable_d3hot(struct device *dev)
@@ -330,4 +330,4 @@ struct chip_operations southbridge_intel_lynxpoint_ops = {
 	.enable_dev = pch_enable,
 };
 
-#endif /* __SMM__ */
+#endif /* __SIMPLE_DEVICE__ */
diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c
index bc86053eca..3e50beeb09 100644
--- a/src/southbridge/intel/lynxpoint/usb_ehci.c
+++ b/src/southbridge/intel/lynxpoint/usb_ehci.c
@@ -24,7 +24,7 @@
 #include <device/pci_ops.h>
 #include "pch.h"
 
-#ifdef __SMM__
+#ifdef __SIMPLE_DEVICE__
 
 void usb_ehci_disable(pci_devfn_t dev)
 {
@@ -132,7 +132,7 @@ void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ)
 	}
 }
 
-#else /* !__SMM__ */
+#else /* !__SIMPLE_DEVICE__ */
 
 static void usb_ehci_clock_gating(struct device *dev)
 {
@@ -202,4 +202,4 @@ static const struct pci_driver pch_usb_ehci __pci_driver = {
 	.devices = pci_device_ids,
 };
 
-#endif /* !__SMM__ */
+#endif /* !__SIMPLE_DEVICE__ */
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index 686e06a6a9..4818d626f0 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -166,7 +166,7 @@ static void usb_xhci_reset_usb3(struct device *dev, int all)
 		usb_xhci_reset_status_usb3(mem_base, port);
 }
 
-#ifdef __SMM__
+#ifdef __SIMPLE_DEVICE__
 
 /* Handler for XHCI controller on entry to S3/S4/S5 */
 void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ)
@@ -251,7 +251,7 @@ void usb_xhci_route_all(void)
 	usb_xhci_reset_usb3(PCH_XHCI_DEV, 1);
 }
 
-#else /* !__SMM__ */
+#else /* !__SIMPLE_DEVICE__ */
 
 static void usb_xhci_clock_gating(struct device *dev)
 {
@@ -395,4 +395,4 @@ static const struct pci_driver pch_usb_xhci __pci_driver = {
 	.vendor	 = PCI_VENDOR_ID_INTEL,
 	.devices = pci_device_ids,
 };
-#endif /* !__SMM__ */
+#endif /* !__SIMPLE_DEVICE__ */