src/southbridge: Drop unneeded empty lines

Change-Id: I02aa1e2a9a9061b34b91f832d96123a8595d61b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>

5 files changed, 0 insertions, 13 deletions

diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h
index cba7671ecc..e30d4b4c21 100644
--- a/src/southbridge/intel/lynxpoint/chip.h
+++ b/src/southbridge/intel/lynxpoint/chip.h
@@ -91,5 +91,4 @@ struct southbridge_intel_lynxpoint_config {
 	bool docking_supported;
 };
 
-
 #endif				/* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c
index c85ba2c616..448ee8bd68 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.c
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.c
@@ -19,7 +19,6 @@ static u16 get_gpio_base(void)
 #endif
 }
 
-
 /*
  * This function will return a number that indicates which PIRQ
  * this GPIO maps to.  If this is not a PIRQ capable GPIO then
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index a9fa61fb43..e5614303cc 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -791,7 +791,6 @@ static struct device_operations device_ops = {
 	.ops_pci		= &pci_dev_ops_pci,
 };
 
-
 /* IDs for LPC device of Intel 8 Series Chipset (Lynx Point) */
 static const unsigned short pci_device_ids[] = {
 	0x8c41, /* Mobile Full Featured Engineering Sample. */
diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c
index 8c4a8c1c90..af7a2b2b98 100644
--- a/src/southbridge/intel/lynxpoint/pmutil.c
+++ b/src/southbridge/intel/lynxpoint/pmutil.c
@@ -57,7 +57,6 @@ static void print_gpio_status(u32 status, int start)
 	}
 }
 
-
 /*
  * PM1_CNT
  */
@@ -78,7 +77,6 @@ void disable_pm1_control(u32 mask)
 	outl(pm1_cnt, get_pmbase() + PM1_CNT);
 }
 
-
 /*
  * PM1
  */
@@ -127,7 +125,6 @@ void enable_pm1(u16 events)
 	outw(events, get_pmbase() + PM1_EN);
 }
 
-
 /*
  * SMI
  */
@@ -198,7 +195,6 @@ void disable_smi(u32 mask)
 	outl(smi_en, get_pmbase() + SMI_EN);
 }
 
-
 /*
  * ALT_GP_SMI
  */
@@ -298,7 +294,6 @@ void enable_alt_smi(u32 mask)
 	}
 }
 
-
 /*
  * TCO
  */
@@ -368,7 +363,6 @@ void enable_tco_sci(void)
 	enable_gpe(TCOSCI_EN);
 }
 
-
 /*
  * GPE0
  */
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 5ccb229805..f5c5f2a80e 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -78,7 +78,6 @@ static void busmaster_disable_on_bus(int bus)
 	}
 }
 
-
 static void southbridge_smi_sleep(void)
 {
 	u8 reg8;
@@ -379,8 +378,6 @@ static void southbridge_smi_mc(void)
 	printk(BIOS_DEBUG, "Microcontroller SMI.\n");
 }
 
-
-
 static void southbridge_smi_tco(void)
 {
 	u32 tco_sts = clear_tco_status();
@@ -443,7 +440,6 @@ static void southbridge_smi_monitor(void)
 			mask |= (0xff << ((i - 16) << 2));
 	}
 
-
 	/* IOTRAP(3) SMI function call */
 	if (IOTRAP(3)) {
 		if (gnvs && gnvs->smif)