diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2012-10-31 23:05:25 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-14 06:35:48 +0100 |
| commit | 89f79a019fd049f26ed7bf40618ff960bd9e095e (patch) | |
| tree | e3bf2a39fe6f4d9f2570a4373376aeefbf7a3664 /src/southbridge/intel/lynxpoint/smihandler.c | |
| parent | b9ea8b3fb0082840b0c9d449535f4c49c2e885ac (diff) | |
haswell: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.
Change-Id: I8406cec16c1ee1bc205b657a0c90beb2252df061
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2618
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/smihandler.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/smihandler.c | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index c5c2c3ec15..d31e350b76 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -38,7 +38,6 @@ * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ #include <northbridge/intel/haswell/haswell.h> -#include <northbridge/intel/haswell/pcie_config.c> /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value @@ -65,7 +64,7 @@ static u32 tseg_base = 0; u32 smi_get_tseg_base(void) { if (!tseg_base) - tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1; + tseg_base = pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1; return tseg_base; } void tseg_relocate(void **ptr) @@ -302,7 +301,7 @@ static void southbridge_gate_memory_reset(void) u32 reg32; u16 gpiobase; - gpiobase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; + gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; if (!gpiobase) return; @@ -388,13 +387,13 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat /* Always set the flag in case CMOS was changed on runtime. For * "KEEP", switch to "OFF" - KEEP is software emulated */ - reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); if (s5pwr == MAINBOARD_POWER_ON) { reg8 &= ~1; } else { reg8 |= 1; } - pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); + pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); /* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); @@ -625,7 +624,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ if (tco_sts & (1 << 8)) { // BIOSWR u8 bios_cntl; - bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); + bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); if (bios_cntl & 1) { /* BWE is RW, so the SMI was caused by a @@ -639,7 +638,7 @@ static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ @@ -766,7 +765,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav u32 smi_sts; /* Update global variable pmbase */ - pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. |