diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 23:23:16 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-15 08:33:30 +0200 |
| commit | da5f5094f04ce8a5a15f89ce39e291cf723773fd (patch) | |
| tree | 59df27f009ee0d07900a0c0fac71a7897972f4e8 /src/southbridge/intel/lynxpoint/pch.h | |
| parent | 340898f21a94922a43b68d49a4f1bbd1f03d622e (diff) | |
southbridge/intel/lynxpoint: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions
generic ACPI definitions.
BUG=chrome-os-partner:54977
Change-Id: I03051c1c1df3e64abeedd6370a440111ade59742
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15676
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.h')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 2b834ff439..a3cd811c7a 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -17,6 +17,8 @@ #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H #define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H +#include <arch/acpi.h> + /* * Lynx Point PCH PCI Devices: * @@ -696,13 +698,6 @@ void pch_enable_lpc(void); #define GBL_EN (1 << 5) #define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 #define GBL_RLS (1 << 2) #define BM_RLD (1 << 1) #define SCI_EN (1 << 0) |