From da5f5094f04ce8a5a15f89ce39e291cf723773fd Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 13 Jul 2016 23:23:16 -0500 Subject: southbridge/intel/lynxpoint: use common Intel ACPI hardware definitions Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I03051c1c1df3e64abeedd6370a440111ade59742 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/15676 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: Furquan Shaikh --- src/southbridge/intel/lynxpoint/pch.h | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'src/southbridge/intel/lynxpoint/pch.h') diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 2b834ff439..a3cd811c7a 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -17,6 +17,8 @@ #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H #define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H +#include + /* * Lynx Point PCH PCI Devices: * @@ -696,13 +698,6 @@ void pch_enable_lpc(void); #define GBL_EN (1 << 5) #define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 #define GBL_RLS (1 << 2) #define BM_RLD (1 << 1) #define SCI_EN (1 << 0) -- cgit v1.2.3