diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2012-10-31 23:05:25 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-14 06:35:48 +0100 |
| commit | 89f79a019fd049f26ed7bf40618ff960bd9e095e (patch) | |
| tree | e3bf2a39fe6f4d9f2570a4373376aeefbf7a3664 /src/southbridge/intel/lynxpoint/me_9.x.c | |
| parent | b9ea8b3fb0082840b0c9d449535f4c49c2e885ac (diff) | |
haswell: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.
Change-Id: I8406cec16c1ee1bc205b657a0c90beb2252df061
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2618
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/me_9.x.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/me_9.x.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index facfc37645..12f7ab7ed2 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -39,7 +39,6 @@ #ifdef __SMM__ # include <arch/romcc_io.h> -# include <northbridge/intel/haswell/pcie_config.c> #else # include <device/device.h> # include <device/pci.h> @@ -496,14 +495,14 @@ void intel_me_finalize_smm(void) u32 reg32; mei_base_address = - pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; + pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; /* S3 path will have hidden this device already */ if (!mei_base_address || mei_base_address == 0xfffffff0) return; /* Make sure ME is in a mode that expects EOP */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); memcpy(&hfs, ®32, sizeof(u32)); /* Abort and leave device alone if not normal mode */ @@ -516,10 +515,10 @@ void intel_me_finalize_smm(void) mkhi_end_of_post(); /* Make sure IO is disabled */ - reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND); + reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); |