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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-29 23:14:53 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-02-06 07:16:16 +0000
commit8fee9951d30d03b4bca16c198b887c5415418c12 (patch)
tree929be61cb85aee7c83bcc4e91f82ef379e960b60 /src/southbridge/intel/lynxpoint/include/soc/nvs.h
parent68d68f1d7c7693f7e49634b6c2106d3c2630d4b0 (diff)
sb,soc/intel: Add wake source fields in GNVS
For the moment, these are most not used but become a necessity for a unified <soc/nvs.h> approach. They would be required for the implementation of _SWS method for OSPM to determine the reason for system waking up. The related hardware registers are present with these platforms. It's expected that ACPI power-management related GNVS entries are grouped together to form a single struct in later works. Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50193 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/include/soc/nvs.h')
-rw-r--r--src/southbridge/intel/lynxpoint/include/soc/nvs.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/include/soc/nvs.h b/src/southbridge/intel/lynxpoint/include/soc/nvs.h
index 17ded13589..7db206e6e9 100644
--- a/src/southbridge/intel/lynxpoint/include/soc/nvs.h
+++ b/src/southbridge/intel/lynxpoint/include/soc/nvs.h
@@ -73,6 +73,10 @@ struct __packed global_nvs {
u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */
u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */
u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */
+
+ /* Required for future unified acpi_save_wake_source. */
+ u32 pm1i;
+ u32 gpei;
};
#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H */