diff options
author | Angel Pons <th3fanbus@gmail.com> | 2022-05-06 23:43:46 +0200 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-16 17:15:53 +0000 |
commit | 49509189dc13d467ac2ec2a63b75e30d5f93c9a7 (patch) | |
tree | 1b845e0051b6188ed7eace6e034a97be23882483 /src/southbridge/intel/lynxpoint/hsio/common.c | |
parent | 9c8c858e687e03e19773ea84fea021301de0e933 (diff) |
sb/intel/lynxpoint: Add native PCH init
Implement native PCH initialisation for Lynx Point. This is only needed
when MRC.bin is not used.
Change-Id: I36867bdc8b20000e44ff9d0d7b2c0d63952bd561
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/hsio/common.c')
-rw-r--r-- | src/southbridge/intel/lynxpoint/hsio/common.c | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/hsio/common.c b/src/southbridge/intel/lynxpoint/hsio/common.c new file mode 100644 index 0000000000..111e6bd35c --- /dev/null +++ b/src/southbridge/intel/lynxpoint/hsio/common.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <device/pci_ops.h> +#include <southbridge/intel/lynxpoint/hsio/hsio.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <types.h> + +/** + * FIXME: Ask Intel whether all lanes need to be programmed as specified + * in the PCH BWG. If not, make separate tables and only check this once. + */ +void hsio_sata_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or) +{ + const uint8_t lane_owner = pci_read_config8(PCH_PCIE_DEV(0), 0x410); + + if ((addr & 0xfe00) == 0x2000 && (lane_owner & (1 << 4))) + return; + + if ((addr & 0xfe00) == 0x2200 && (lane_owner & (1 << 5))) + return; + + if (CONFIG(INTEL_LYNXPOINT_LP)) { + if ((addr & 0xfe00) == 0x2400 && (lane_owner & (1 << 6))) + return; + + if ((addr & 0xfe00) == 0x2600 && (lane_owner & (1 << 7))) + return; + } + hsio_update(addr, and, or); +} + +void hsio_xhci_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or) +{ + const uint8_t lane_owner = pci_read_config8(PCH_PCIE_DEV(0), 0x410); + if (CONFIG(INTEL_LYNXPOINT_LP)) { + if ((addr & 0xfe00) == 0x2400 && ((lane_owner >> 0) & 3) != 2) + return; + + if ((addr & 0xfe00) == 0x2600 && ((lane_owner >> 2) & 3) != 2) + return; + } else { + if ((addr & 0xfe00) == 0x2c00 && ((lane_owner >> 2) & 3) != 2) + return; + + if ((addr & 0xfe00) == 0x2e00 && ((lane_owner >> 0) & 3) != 2) + return; + } + hsio_update(addr, and, or); +} |