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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-07-20 08:50:38 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-07-22 05:38:38 +0200
commita27fba67a0dc8f2d2b991b08dbcd2eb485baa8d7 (patch)
tree7baa8a36fc6b32cb94b8a7f8e5757c4ddf55d1e1 /src/southbridge/intel/lynxpoint/finalize.c
parent81527e8d7ff4fc3b0480349b934807bcf4c78c55 (diff)
intel model_106cx: Include CAR from socket directory
Since the socket layer is implemented with this CPU model, there could potentially be multiple CPU models included. There can be only one cache_as_ram include, so select it directly within the socket directory. Change-Id: Ia52bb152276eddfd1fb33ddb7f5d153ab8e8163c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15757 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/finalize.c')
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