diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-12 13:06:45 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-15 06:00:31 +0000 |
| commit | 30931f5a4d67571ab8138777647d1d7f29ca3671 (patch) | |
| tree | cdb09228ea8565f738ef525f40dc683b2c1810b6 /src/southbridge/intel/lynxpoint/early_pch.c | |
| parent | 0b39379c9c85d693b74ae7e954298bc4760285f3 (diff) | |
sb/intel/lynxpoint: Move S3 check out of `early_pch_init`
Done for consistency with other platforms. This also drops redundant S3
resume logging, as `southbridge_detect_s3_resume` already prints it.
Tested on Asrock B85M Pro4, still boots and still resumes from S3.
Change-Id: Id96c5aedad80702ebf343dd0a351fbd4e7b1c6c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/early_pch.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_pch.c | 12 |
1 files changed, 1 insertions, 11 deletions
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 2d0a53d799..66a3205c3b 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -6,7 +6,6 @@ #include <device/pci_def.h> #include <device/smbus_host.h> #include <southbridge/intel/common/pmbase.h> -#include <southbridge/intel/common/pmclib.h> #include <elog.h> #include "pch.h" #include "chip.h" @@ -86,10 +85,8 @@ void __weak mainboard_config_superio(void) { } -int early_pch_init(void) +void early_pch_init(void) { - int wake_from_s3; - pch_enable_bars(); #if CONFIG(INTEL_LYNXPOINT_LP) @@ -123,11 +120,4 @@ int early_pch_init(void) RCBA32(0x2324) = 0x00854c74; } - - wake_from_s3 = southbridge_detect_s3_resume(); - - elog_boot_notify(wake_from_s3); - - /* Report if we are waking from s3. */ - return wake_from_s3; } |