diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-11-04 17:47:45 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-26 07:30:22 +0000 |
| commit | 2cdf8bdb61479391f3df69360724e0b3510f7c6f (patch) | |
| tree | 3eb4a76f296d6d09aa56171ac2bebe146fa92bbc /src/southbridge/intel/lynxpoint/early_pch.c | |
| parent | 68220b5c429e0205f5f73758ce4b078696dc5388 (diff) | |
sb/intel/lynxpoint: Update LPT-H magic as per RC 1.9.1
Add the missing PM initialization for Lynxpoint-H. There are some small
changes to Lynxpoint-LP, since some register writes are common among
both PCH variants. This is based on version 1.9.1 of reference code.
Remove the `pch_fixups()` function. The DMI configuration is specific to
Lynxpoint-H. It is not valid for Lynxpoint-LP, which does not have DMI.
Tested on Asrock B85M Pro4, still boots. Registers have the new values.
Without this patch, nearly all registers don't have the expected values.
Change-Id: Ie3f96f2106f3c23aeb694dd6fb343099fc5784e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47208
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/early_pch.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_pch.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 75aaf67737..2d0a53d799 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -113,6 +113,17 @@ int early_pch_init(void) RCBA32_OR(FD, PCH_DISABLE_ALWAYS); + RCBA32(0x2088) = 0x00109000; + + RCBA32_OR(0x20ac, 1 << 30); + + if (!pch_is_lp()) { + RCBA32_AND_OR(0x2340, ~(0xff << 0), 0x1b << 0); + RCBA32_AND_OR(0x2340, ~(0xff << 16), 0x3a << 16); + + RCBA32(0x2324) = 0x00854c74; + } + wake_from_s3 = southbridge_detect_s3_resume(); elog_boot_notify(wake_from_s3); |